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74AC109-2001 数据手册 ( 数据表 )

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The MC74AC109/74ACT109 consists of two high–speed completely independent transition clocked JK flip–flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip–flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs

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DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
Dual JK Positive Edge-Triggered Flip-Flop
Fairchild Semiconductor
Dual JK Positive Edge-Triggered Flip-Flop
AVG Semiconductors=>HITEK
Dual JK positive edge-triggered flip-flop
Motorola => Freescale
Dual JK Positive Edge−Triggered Flip−Flop
ON Semiconductor
Dual JK negative edge-triggered flip-flop
Motorola => Freescale
Dual JK Negative Edge-Triggered Flip-Flop
Hitachi -> Renesas Electronics
Dual JK Positive Edge-Triggered Flip-Flop
Fairchild Semiconductor
Dual JK Negative Edge-Triggered Flip-Flop
AVG Semiconductors=>HITEK

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