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74F109 数据手册 ( 数据表 )

零件编号
产品描述 (功能)
生产厂家
74F109
Fairchild
Fairchild Semiconductor Fairchild
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General Description
The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes
      both Q and Q HIGH

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零件编号
产品描述 (功能)
PDF
生产厂家
Dual JK Positive Edge-Triggered Flip-Flop
ON Semiconductor
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
Dual JK Positive Edge-Triggered Flip-Flop
ON Semiconductor
Dual JK Positive Edge-Triggered Flip-Flop
AVG Semiconductors=>HITEK
Dual JK positive edge-triggered flip-flop
Motorola => Freescale
Dual JK Positive Edge−Triggered Flip−Flop
ON Semiconductor
Dual JK negative edge-triggered flip-flop
Motorola => Freescale
Dual JK Negative Edge-Triggered Flip-Flop
Hitachi -> Renesas Electronics
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale

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