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74F112 数据手册 ( 数据表 )

零件编号产品描述 (功能)生产厂家
74F112 Dual JK Negative Edge-Triggered Flip-Flop Fairchild
Fairchild Semiconductor Fairchild
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General Description
The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and Q HIGH.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH

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与其他制造商的搜索 '74F112'

零件编号产品描述 (功能)PDF生产厂家
HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop 视图 Hitachi -> Renesas Electronics
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MC74F112D DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP 视图 Motorola => Freescale
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74LS73 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY 视图 Motorola => Freescale
SN54LS113A Dual JK negative edge-triggered flip-flop 视图 Motorola => Freescale
74LS112 Dual JK negative edge-triggered flip-flop 视图 Motorola => Freescale
SN54LS73 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP 视图 Motorola => Freescale

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