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Dual Asychronous Receiver/Transmitter

The MC2681 dual universal asychronous Receiver/Transmitter (DUART) is part of the MC68000 Family  of peripherals and directly interfaces to the MC68000 processor via a general-purpose interface that may be used with both sychronous and asychronous microprocessors.

DESCRIPTION

The Philips Semiconductors SCC68692 Dual Universal Asynchronous Receiver/Transmitter (DUART) is compatible with SCN68681. It is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous Receiver/Transmitter channels in a single package. It is compatible with other S68000 family devices and can also interface easily with other microprocessors. The DUART can be used in a polled or interrupt driven systems.

DESCRIPTION

The SCC2698B Enhanced Octal Universal Asynchronous Receiver/Transmitter (Octal UART) is a single chip MOS-LSI communications device that provides eight full-duplex asynchronous Receiver/Transmitter channels in a single package. It is fabricated with CMOS technology which combines the benefits of high density and low power consumption.

INTRODUCTION
The MC68HC681 dual universal asynchronous Receiver/Transmitter (DUART) is part of the M68000 Family of peripherals and directly interfaces to the MC68000 processor via an asynchronous bus structure. The MC68HC681 consists of these major sections:

   • Internal Control Logic
   • Timing Logic
   • Interrupt Control Logic
   • Bidirectional 8-bit Data Bus Buffer
   • Two Independent Communication Channels (A and B)
   • 6-bit Parallel Input Port
   • 8-bit Parallel Output Port

The MC68HC2681 dual asynchronous Receiver/Transmitter (DUART) is functionally equivalent to the MC68HC681 with some minor differences. The description of the MC68HC681 applies to the MC68HC2681 except for the areas described in Appendix A MC68HC2681 located in the back of this document.

Figure 1-1 is a basic block diagram of the MC68HC681 and should be referred to during the discussion of its features, which include the following:

• M68000 Bus Compatible
• Two Independent Full-Duplex Asynchronous Receiver/Transmitter Channels
• Maximum Data Transfer Rate:
   — 1X — 1 Mbits/second
   — 16X — 250 kbits/second
• Quadruple-Buffered Receiver Data Registers
• Double-Buffered Transmitter Data Registers
• Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable From:
   — 18 Fixed Rates: 50 to 38.4k Baud
   — One User Defined Rate Derived from a Programmable Timer/Counter
   — External 1X Clock or 16X Clock

ARINC629 Receiver Transmitter

General Description
The a6402 MegaCore function implements a universal asynchronous Receiver/Transmitter (UART), which provides an interface between a microprocessor and a serial communications channel. See Figure 1.

Features
■ a6402 MegaCore function implementing a universal asynchronous
   Receiver/Transmitter (UART)
■ Optimized for FLEX® and MAX® architectures
■ Uses approximately 162 FLEX logic elements (LEs)
■ Programmable word length, stop bits, and parity
■ Full duplex operation
■ Includes status flags for parity, framing, and overrun errors
■ Functionally based on the Harris HD-6402 device, except as noted in
   the “Variations & Clarifications” section on page 63

DESCRIPTION
The STB4395(A) is a fully integrated ReceiverTransmitter designed for CT2 applications, and incorporates all the VCO’s, synthesizers, PLLs, and channel select logic, to make a fully functional ”single chip” radio.

■ FULLY INTEGRATED DOUBLE SUPERHETERODYNE Receiver
■ OPERATION FROM 800MHz TO 1000MHz
■ Receiver OUTPUT AS BITSTREAM
■ FULLY INTEGRATED Transmitter
■ Transmitter INPUT I/Q/REFIQ OR I/I, Q/Q
■ INTEGRATED POWER AMPLIFIER
■ CT2 PA SWITCH-ON PROFILE INTEGRATED
■ VCO’s INTEGRATED
■ SYNTHESIZERS INTEGRATED
■ CHANNEL SELECT LOGIC ON CHIP
■ INTEGRATED VOLTAGE REGULATION
■ SUPPLY VOLTAGES FROM 3.0V TO 5.5V

GENERAL DESCRIPTION
The HI-8282A is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two Receivers and an independent Transmitter are provided. The Receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The Transmitter section provides the ARINC 429 communication protocol. Additional interface circuitry such as the Holt HI-8585, HI-8586 or HI-3182 is required to translate the 5 volt logic outputs to ARINC 429 drive levels.

FEATURES
• ARINC specification 429 compatible
• 16-Bit parallel data bus
• Direct Receiver interface to ARINC bus
• Timing control 10 times the data rate
• Selectable data clocks
• Receiver error rejection per ARINC specification 429
• Automatic Transmitter data timing
• Self test mode
• Parity functions
• Low power, single 5 volt supply
• Industrial & full military temperature ranges

Universal Asynchronous Receiver Transmitter

DESCRIPTION
The Epic Ei16C450 Universal Asynchronous Receiver Transmitter (UART) is a CMOS-VLSI communication device in a single package.

FEATURES
• 5V Operation
• Full duplex asynchronous Receiver and Transmitter
• Easily interfaces to most popular microprocessors
• Adds or deletes standard asynchronous communication bits (start, stop, and parity ) to or from a serial data stream
• Independently controlled Transmitter, Receiver, line status, and data set interrupts
• Programmable baud rate generator allows division of any input clock by 1 to (216-1) and generates the internal 16 x clock
• Independent Receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Fully programmable serial interface characteristics:
    - 5, 6, 7, or 8 bit characters
    - Even, odd, or no-parity bit generation and detection
    - 1, 1.5, or 2 stop bit generation
    - Baud generation (DC to 56k baud)
• False start bit detection
• Complete status reporting capabilities
• Tri-State® TTL drive capabilities for bi-direc tional data bus and control bus
• Line break generation and detection
• Internal diagnostic capabilities:
    - Loopback controls for communications link fault isolation
    - Break, parity overrun, and framing error simulation
• Fully prioritized interrupt systems controls