FS6322-02
Three-PLL Clock Generator IC
1.0 Features
• Three PLLs with deep reference, feedback, and post
dividers to provide precision clock frequencies
• Multiple outputs provide several clocking options
• Suspend feature shuts down a selection of PLLs and
outputs for power conservation
• Outputs may be tristated for board testing
• S0 and S1 frequency select inputs modify output fre-
quencies for design flexibility
• Glitch-free slewing of CLK_CPU output enables
downstream PLLs to remain locked
• 5V to 3.3V operation
• Accepts 5 to 30MHz crystals
• Custom frequency patterns, pinouts, and packages
are available. Contact your local AMI Sales Repre-
sentative for more information.
2.0 Description
The FS6322 is a ROM-based CMOS clock generator IC
designed to minimize cost and component count in a va-
riety of electronic systems.
Three low-jitter phase-locked loops (PLLs) drive up to five
low-skew clock outputs to provide a high degree of flexi-
bility. A buffered copy of the reference clock is also avail-
able. The device is packaged in a 16-pin SOIC to mini-
mize board space.
Figure 1: Pin Configuration
CLK_C 1
VDD 2
VSS 3
XIN 4
XOUT 5
XBUF 6
CLK_D 7
CLK_CPU 8
16 OE
15 SUSPEND#
14 VDD
13 S1
12 S0
11 VSS
10 CLK_A
9 CLK_B
16-pin (0.150”) SOIC
Figure 2: Block Diagram
OE
XIN
XOUT
Crystal
Oscillator
S1:S0
SUSPEND#
PLL A
PLL B
PLL CPU
Clock
Logic
FS6322
XBUF
CLK_A
CLK_B
CLK_C
CLK_D
CLK_CPU
This document contains information on a product under development. American Microsystems, Inc. reserves the right to change or discontinue this product without notice.
ISO9001
3.1.02