Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC / PLL)
Timer A
4
Quadrature Decoder 0
4
Timer D
Timer B
4
Quadrature Decoder 1
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
SIM
RESET
COP Reset
COP
FlexCAN
2
SPI1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
4
SPI0
2
SCI0
2
SCI1
IPBus
NOT available on the 56F8135 device.
PWMA
PWMB
13
SYNC Output
13
SYNC Output
ch3i
ch2i
2
Timer C
ch3o
ch2o
ADCB
8
ADCA
8
TEMP_SENSE 1
Note: ADC A and ADC B use the same
voltage reference circuit with VREFH,
VREFP, VREFMID, VREFN, and VREFLO
pins.
Figure 1-2 Peripheral Subsystem
56F8335 Technical Data, Rev. 5
Freescale Semiconductor
11
Preliminary