Smart High-Side Power Switch
BTS724G
Truth Table
Channel 1 and 2
Chip 1
IN1 IN2 OUT1 OUT2
Channel 3 and 4
Chip 2
IN3 IN4 OUT3 OUT4
(equivalent to channel 1 and 2)
Normal operation
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
Open load
Channel 1 (3) L
X
Z
X
H
X
H
X
Channel 2 (4) X
L
X
Z
X
H
X
H
Overtemperature
both channel
L
L
L
L
X
H
L
L
H
X
L
L
Channel 1 (3) L
X
L
X
H
X
L
X
Channel 2 (4) X
L
X
L
X
H
X
L
ST1/2
ST3/4
H
H
H
H
L20)
H
L15)
H
H
L
L
H
L
H
L
L = "Low" Level
H = "High" Level
X = don't care
Z = high impedance, potential depends on external circuit
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
,EE
9EE
, ,1
, ,1
, 67
9,1 9,1 967
/HDGIUDPH
,1
9EE
,1
352)(7
&KLS
67 *1'
5 *1'
287
287
,*1'
921
921
, /
, /
9287
9287
, ,1
, ,1
, 67
9,1 9,1 967
/HDGIUDPH
,1
9EE
,1
352)(7
&KLS
67 *1'
5 *1'
287
287
,*1'
921
921
, /
, /
9287
9 287
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.
20) L, if potential at the Output exceeds the OpenLoad detection voltage
Data Sheet
8
V1.0, 2007-05-13