G150X1-L01 查看數據表（PDF） - AZ Displays
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G150X1-L01 Datasheet PDF : 27 Pages
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Doc No.: 14066727
Issued Date: Feb. 8, 2007
Model No.: G150X1-L01
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Item
Symbol Min. Typ. Max. Unit Note
DCLK
DE
Pixel Clock
Vertical Total Time
Vertical Address Time
Horizontal Total Time
Horizontal Address Time
1/TC
-
65
80 MHz
-
TV
780 806 1200
TH
-
TVD
768 768 768
TH
-
TH
1140 1344 1600
TC
-
THD
1024 1024 1024
TC
-
Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
DE
DCLK
DE
DATA
INPUT SIGNAL TIMING DIAGRAM
Tv
TVD
TH
TC
THD
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Version 2.2
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