NX25F080A
Transfer Program Buffer to SRAM
The Transfer Program Buffer to SRAM command (55H)
provides access to the 536-Byte Program Buffer. The
command sequence is similar to the Write or Read SRAM
commands except that the sector address field S[15:0]
and byte address B[15:0] field are replaced with all 0 bits.
After the last byte address is transferred, the command is
completed by issuing 16 control clocks and then asserting
Transfer Program
Buffer to SRAM
Command 16 Clocks
16 Clocks
16 Clocks
SI
55H
0000H
0000H
0000H
CS high. There is a delay time after CS is asserted high
1 (see tXP timing specification). During this time the data
from the Program Buffer is being transferred to the SRAM
and neither are available for use. Status of this operation
can be checked by testing the Transfer in Process bit (TR)
2 in the Status Register. This command cannot be used
while the device is busy.
Transfer Time
3
(tXP)
SO
4
5
CONFIGURATION AND STATUS
COMMANDS
6
Read Configuration Register
The Read Configuration Register command provides
access to the Configuration Register, which stores the
current configuration of the HOLD-R/B pin, read clock
edge, write protect range, and alternate oscillator
frequency (Figure 6). The command sequence is similar
to the Read from Sector command except that the sector
address field S[15:0] and the byte-address field B[15:0]
Read Configuration
Register
Command 16 Clocks
16 Clocks
16 Clocks
SI
8BH
0000H
0000H
0000H
7 are replaced with all 0 bits. After 16 control clocks and
after the Ready/Busy status field has been clocked
through, a 16-bit configuration data field CF[15:0]
provides the contents of the Configuration Register.
8 Although the field is 16-bits long, only bits CF[8:0] are
used. All other upper bits are reserved for future
features.
9
SO
*The CF Register only uses bits [8:0]
RB[15:0]
CF{15:0}*
10
Read/Busy
Status
Read Configuration Bits
11
12
NexFlash Technologies, Inc.
17
PRELIMINARY NXSF005C-0699
06/11/99 ©