WM8955 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8955 Datasheet PDF : 43 Pages
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WM8955L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
SYMBOL
tMCLKL
tMCLKH
tMCLKY
MIN
TYP
MAX
16
16
27
UNIT
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
DACLRC
(Output)
DACDAT
tDST
tDL
tDHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
System Clock Timing Information
DACLRC propagation delay from BCLK falling edge
tDL
10
DACDAT setup time to BCLK rising edge
tDST
10
DACDAT hold time from BCLK rising edge
tDHT
10
UNIT
ns
ns
ns
BCLK
DACLRC
DACDAT
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
tBCY
tDS
tLRH
tLRSU
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
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Product Preview Rev 0.4 May 2003
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