HMS91C7432 查看數據表（PDF） - Hynix Semiconductor

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HMS91C7432

HMS91C7432 features and functions

Hynix Semiconductor 

Hynix semiconductor

Specifications of HMS91C7432

WR

Strobe

Wait

Data[7:0]

12

3

45 6

Valid data

Figure 1. Data Write Cycle waveform

Data Write cycle phase transitions:

1. The Write line is asserted and the data is output to the parallel port

2. The data strobe is asserted, since WAIT is asserted low

3. The port waits for the acknowledge from the HMS91C7432 (WAIT de-asserted)

4. The data strobe is de-asserted

5. The write cycle ends

6. WAIT is asserted low to indicate that the next cycle may begin

12

3

4

5

WR

Strobe

Wait

Data[7:0]

Valid data

Figure 2. Data Read Cycle waveform

Data Read cycle phase transitions:

1. The Write line is set to HIGH to indicate read request

2. The data strobe is asserted, since WAIT is asserted low

3. The port waits for the acknowledge from the HMS91C7432 (WAIT de-asserted)

4. The data strobe is de-asserted after data is stored and the read cycle ends

5. WAIT is asserted low to indicate that the next cycle may begin

5

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