AR0141CS
GENERAL DESCRIPTION
The ON Semiconductor AR0141CS can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
720p−resolution image at 60 frames per second (fps). In
linear mode, it outputs 12−bit raw data, using either the
parallel or serial (HiSPi) output ports. The device may be
operated in video (master) mode or in single frame trigger
mode.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0141CS includes additional features to allow
application−specific tuning: windowing and offset, auto
black level correction, and on−board temperature sensor.
Optional register information and histogram statistic
information can be embedded in the first and last 2 lines of
the image frame.
FUNCTIONAL OVERVIEW
The AR0141CS is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can be
optionally enabled to generate all internal clocks from a
ADC data
single master input clock running between 6 and 50 MHz.
The maximum output pixel rate is 148.5 Mp/s,
corresponding to a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor.
Row noise correction
Black level correction
Test pattern generator
Pixel defect correction
Adaptive CD filter
12 or 10 bits
Parallel
12 bits
HiSPi
Digital gain and
pedestal
Figure 1. Block Diagram
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.1 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain).
www.onsemi.com
3