Preface
Timing diagram conventions
The key provided in Figure P-1 explains the components used in timing diagrams. Any
variations are labeled when they occur. Therefore, no additional meaning must be
attached unless specifically stated.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure P-1 Key to timing diagram conventions
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ARM DDI 0029G