SEMICONDUCTOR
IRF150 Series RRooHHSS
Nell High Power Products
Fig.12c. Maximum avalanche energy vs.
Drain current
1000
800
TOP
lD
9.0A
16A
BOTTOM 22A
600
400
200
0
25
50 75 100 125 150 175
Starting Junction temperature, TJ (°C)
Fig.13a. Basic gate charge waveform
Fig.13b. Gate charge test circuit
VGS
10V
QGS
QG
QGD
Charge
Current Regulator
Same Type as D.U.T.
50KΩ
12V
0.2µF
0.3µF
VGS
3mA
D.U.T.
+
VDS
-
RG
RD
Current Sampling Resistors
Fig.14 Peak diode recovery dv/dt test circuit for N-Channel MOSFET
D.U.T.
+ Circuit Layout Considerations
• Low Stray lnductance
• Ground Plane
• Low Leakage lnductance
Current Transformer
-
+
-
+
-
RG
• dv/dt controlled by RG
• Driver same type as D.U.T.
+
• lSD controlled by Duty Factor "D"
VDD
-
• D.U.T. -Device Under Test
Driver Gate Drive
P.W.
Period
P.W.
D=
Period
* VGS=10V
D.U.T. I SD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Re-Applied
Voltage
Body Diode
Inductor Curent
Forward Drop
Ripple ≤ 5%
ISD
*VGS = 5V for Logic Level Devices and 3V for drive devices
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