HI5762/6IN 查看數據表（PDF） - Renesas Electronics
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HI5762/6IN Datasheet PDF : 16 Pages
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HI5762
Electrical Specifications AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = +25°C; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Digital Supply Voltage, DVCC1 and DVCC2
Digital Output Supply Voltage, DVCC3
(Note 4)
At 3.0V (Note 4)
At 5.0V (Note 4)
4.75
5.0
5.25
2.7
3.0
3.3
4.75
5.0
5.25
Supply Current, ICC
Power Dissipation
fS = 60MSPS
-
130
-
-
650
670
Offset Error Sensitivity, VOS
AVCC or DVCC = 5V ±5%
Gain Error Sensitivity, FSE
AVCC or DVCC = 5V ±5%
NOTES:
4. Limits established by characterization and are not production tested.
5. With the clock low and DC input.
-
0.5
-
-
0.6
-
UNITS
V
V
V
mA
mW
LSB
LSB
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2
SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B1, N
B1, N + 1
B2, N - 2
B2, N - 1
B2, N
B1, N + 4
B1, N + 5
B1, N + 6
B1, N + 7
B2, N + 4
B2, N + 5
B2, N + 6
9TH
STAGE
B9, N - 5
B9, N - 4
B9, N
B9, N + 1
B9, N + 2
B9, N + 3
DATA
OUTPUT
DN - 6
DN - 5
DN - 1
DN
tLAT
NOTES:
6. SN: N-th sampling period.
7. HN: N-th holding period.
8. BM, N: M-th stage digital output corresponding to N-th sampled input.
9. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5762 INTERNAL CIRCUIT TIMING
DN + 1
DN + 2
FN4318 Rev 3.00
January 22, 2010
Page 8 of 16
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