29
35
30
36
31
37
32
38
33
39
34
40
41
35
42
36
43
37
44
38
45
39
46
40
47
41
48
42
49,50
43
44
45
46
47-54
55
56-63
64
65-72
73
74
75
76
77
78
79
80
81
51
52,53
54,55
56
57-64
65,66
67-74
75,76
77-84
85
86
87
88
89
90
91
92
93,94
82
95,96
83
97
84
98
2003/4/15
BGNDA
VCC
MDBIAS_GNDA
DPP_VAA1
DPP_GNDA1
CGND
DGND
OSCI
OSCO
NC
HSYNCI
SOGI
VSYNCI
NC
CVDD
NC
CGND
DVDD
DVDD
BB0 ~ BB7
DGND
GB0 ~ GB7
DVDD
RB0- RB7
NC
NC
DGND
NC
NC
DVDD
DISP_DE
DISP_VS
CVDD_CAP
VDD
DISP_HS
NC
11
NT68520X,E
P Front-end analog ground for B
channel
P Display PLL analog power
supply
P Analog power for display PLL
internal bias circuit
P Display PLL analog power
P Display PLL analog ground
P Core logic ground
I Crystal OSC input
O Crystal OSC output
NC pin
I VGA port horizontal sync input
with smith trigger
I VGA port Sync On Green input
with smith trigger
I VGA port vertical sync input
with smith trigger
I Connect to digital ground
P Core logic power de-couple
pin. External capacitor (0.1uF)
Connection is recommended.
NC pin
P Core logic ground
P Display digital power supply
P Display digital power supply
O Port B, B channel output
P Display digital ground
O Port B, G channel output
P Display digital power supply
O Port B, R channel output
NC pin
NC pin
P Display digital ground
P Connect to digital ground
P Connect to digital ground
P Display digital power supply
O Panel display data enable
signal
O Panel display vertical sync
P Internal regulator output pin.
External regulating capacitor
(10uF~100uF) connected is
needed.
P Main power supply for internal
regulator (3.3V)
O Panel display horizontal sync
NC pin
Ver.1.0