• One external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and
GND as close to the chip as possible.
• One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and
GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop. The input decoupling capacitor should be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
5.4 Typical Powering Schematics
The AT91SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input
connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1
shows the power schematics to be used for USB bus-powered systems.
Figure 5-1. 3.3V System Single Power Supply Schematic
VDDFLASH
Power Source
ranges
from 4.5V (USB)
to 18V
DC/DC Converter
3.3V
VDDIO
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
14 AT91SAM7SE512/256/32 Preliminary
6222ES–ATARM–04-Jan-08