The PI6C100 is a high-speed low-noise clock generator designed to work with the PI6C180 clock buffer to meet all clock needs for Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required.
An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system.
• Four copies of CPU clock with VDD of 2.5V + 5%
• 100 MHz or 66 MHz operation
• Eight copies of PCI clock, (synchronous with CPU clock) 3.3V
• Two copies of IO APIC clock @14.31818 MHz
• Two copies of 48 MHz clock
• Three copies of Ref. clock @14.31818 MHz (3.3V TTL)
• Low cost 14.31818 MHz crystal oscillator input
• Spread spectrum modulation of CPU and PCI clocks for reduced EMI
• Power management control
• Isolated core VDD, VSS pins for noise reduction
• 48-pin SSOP package (V48)