SA2030 查看數據表（PDF） - South African Micro Electronic Systems
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SA2030 Datasheet PDF : 40 Pages
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SA9101
Detailed Description
Register
Name
ADR 0
Bit
CR0B0
0
CR0B1
1
CR0B2
2
CR0B3
3
CR0B4
4
CR0B5
5
CR0B6
6
CR0B7
7
ALARM Control
Description
Alarm simulation
A “1” initiates error simulation of alarm indication signal
(AIS), slip, parity, CRC, no signal, loss of frame alignment,
remote alarm, code violations and framing errors.
Error counters for frame errors, code violations and CRC
errors will be incremented.
Force re-synchronisation
Setting of this bit initializes resynchronisation to establish
normal frame alignment and, if enabled, CRC4 frame re-
synchronization.Resetting is not necessary.
Clear CHNL Parity Alarm Latch
Setting of this bit forces reset of CHNL Parity error alarms.
Status-registers ADR 0, bit 2 and ADR 5, bit 3, 4 will be reset
to “0”.
Send AIS towards System interface (DRO), i.e. switching
network (SN). Device sends AIS (continuously one’s) to the
SN. Tests of the speech memory in loopback mode are not
effected.
Disable Error Counters
This bit can be set 1µs before the contents of the error
counters are read to get stable values. The error counters
will be reset after this bit is reset to zero. No errors are
counted while this bit is active. This procedure has been
implemented to maintain compatibility with the previous
frame aligners. If an error counter is read without setting this
bit previously, only the adressed error - counter will be reset
after read -access has been completed.
Enable Control Registers Read
If this bit is set to one, the control registers (ADR0-ADRD) are
selected instead of the status registers during read operation.
Enable Full HDB3-Error Detection
This bit enables HDB3 check for groups of more than 3
spaces (zeros)
Enable Alarm Interrupt Mode
Output DFPY changes its function to AINT while this bit is at
"1”.
Note: All "Not used" bits must be set to zero in all control registers
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