A75 查看數據表（PDF） - Intel

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A75

PENTIUM® PROCESSOR

Intel 

E

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

11. FRCMC# should be tied to VCC (high) to ensure proper operation of the Pentium processor

75/90/100/120/133/150/166/200 as a primary processor.

12. Setup time is required to guarantee recognition on a specific clock. Pentium processor 75/90/100/120/133/150/166/200

must meet this specification for dual processor operation for the FLUSH# and RESET signals.

13. Hold time is required to guarantee recognition on a specific clock. Pentium processor 75/90/100/120/133/150/166/200

must meet this specification for dual processor operation for the FLUSH# and RESET signals.

14. All TTL timings are referenced from 1.5V.

15. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of 2

clocks before being returned active and must meet the minimum pulse width.

16. This input may be driven asynchronously. However, when operating two processors in dual processing mode, FLUSH#

and RESET must be asserted synchronously to both processors.

17. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be de-asserted (inactive) for a minimum

of 2 clocks before being returned active.

18. Timings are valid only when dual processor is present.

19. Maximum time DPEN# is valid from rising edge of RESET.

20. Minimum time DPEN# is valid after falling edge of RESET.

21. The D/C#, M/IO#, W/R#, CACHE#, and A5-A31 signals are sampled only on the CLK that ADS# is active.

22. BF and CPUTYP should be strapped to VCC or VSS.

23. RESET is synchronous in dual processing mode and functional redundancy checking mode. All signals which have a

setup or hold time with respect to a falling or rising edge of RESET in UP mode, should be measured with respect to the

first processor clock edge in which RESET is sampled either active or inactive in dual processing and functional

redundancy checking modes.

24. The PHIT# and PHITM# signals operate at the core frequency.

25. These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the

amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power

spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency. The amount of jitter present must be

accounted for as a component of CLK skew between devices.

26. In dual processing mode, timing t14 is replaced by t83a. Timing t14 is required for external snooping (e.g., address setup to

the CLK in which EADS# is sampled active) in both uniprocessor and dual processor modes.

27. BRDYC# and BUSCHK# are used as reset configuration signals to select buffer size.

28. This assumes an external pullup resistor to VCC and a lumped capacitive load. The pullup resistor must be between 300

ohms and 1k ohms, the capacitance must be between 20 pF and 240 pF, and the RC product must be between 3ns and

36ns. VOL for PICD0-1 is 0.55V.

29. This is a flight time specification, that includes both flight time and clock skew. The flight time is the time from where the

unloaded driver crosses 1.5V (50% of min VCC), to where the receiver crosses the 1.5V level (50% of min VCC). See

Figure 11.

30. This is for the Lock Step operation of the component only. This guarantees that APIC interrupts will be recognized on

specific clocks to support two processors running in a Lock Step fashion, including FRC mode. FRC on the APIC pins is

not supported but mismatches on these pins will result in a mismatch on other pins of the CPU.

31. The CLK to PICCLK ratio for Lock Step operation has to be an integer and the ratio (CLK/PICCLK) cannot be smaller than

4.

* Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer models to account for signal flight

time delays.

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