CXB1572Q 查看數據表（PDF） - Sony Semiconductor
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CXB1572Q Datasheet PDF : 16 Pages
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CXB1572Q
• AC characteristics
(VCC = GND, VEE = –3.0 V to –3.6 V, Ta = –40 to +85 °C, VCC = VCCD, VCCDA, VCCA VEE = VEED, VEEA)
Item
Maximum input voltage amplitude
Symbol
Conditions
Vmax Single-ended input
Min.
Typ.
Max. Unit
1600
mVpp
Amplifier gain
(except for output buffer)
GL
52
dB
Identification maximum voltage
amplitude of alarm level
Hysteresis width
SD response assert time
SD response deassert time
VminA1
SW pin: Low,
single-ended input
20
VminA2
SW pin: Open High,
single-ended input
50
∆P
Alarm level is default
value
3
Tas
Low → High∗1
0
Tdas
High → Low∗2
2.3
SD response assert time for alarm
level default
Tasd
Low → High∗3
0
mVpp
6
7
dB
100
100
µs
100
SD response deassert time for alarm Tdasd
level default
Alarm setting level 1 for default
Vdef1
Alarm setting level 2 for default
Propagation delay time
Vdef2
TPD
High → Low∗4
2.3
UP,DOWN,VEEI pins
;Open,connect SW pin 4.3
to VEE
UP,DOWN,SW pins
;Open,connect VEEI to 10.5
VEE
D to Q
1.2
100
5.3
6.3
mV
12.0
13.5
1.7
2.6
Q/Q SD/SD rise time
Q/Q SD/SD fall time
Tr
RT1 = 50 Ω, VT1 =
0.45
0.85
1.3
VCC–2 V termination,
VEE=–3.3 V,
ns
Ta=0 to 85 °C
Tf
20 % to 80 %
0.45
0.85
1.3
∗1 VUP – VDOWN = 100 mV, Vin = 100 mVpp (single ended), SW pin: High
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗2 VUP – VDOWN = 100 mV, Vin = 1 Vpp (single ended), SW pin: High
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗3 Vin = 50 mVpp (single ended), SW pin: Low
Peak hold capacitance of 470 pF; connect VEEI to VEE.
∗4 Vin = 1 Vpp (single ended), SW pin: Low
Peak hold capacitance of 470 pF; connect VEEI to VEE.
—7—
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