Quad Digital Control Amplifier
4.1.2 Timing
Timing (Figure 3)
Serial Clock "High" Pulse Width
Serial Clock "Low" Pulse Width
Data Set-up Time
Data Hold Time
Load/Latch Pulse Width
Load/Latch Delay
Load/Latch Over
Serial Data Clock Frequency
7
(tPWH)
(tPWL)
(tDS)
(tDH)
(tLLW)
(tLLD)
(tLLO)
Min.
250
250
150
50.0
150
200
Typ. Max.
0.0
2.0
MX019
Units
ns
ns
ns
ns
ns
ns
ns
MHz
SERIAL DATA CLOCK
SERIAL DATA IN
(ONE 8-BIT WORD)
t PWL
t DS
t PWH
tDH
8th
Clock
Pulse
Logic '1'
Loaded
First
BIT 7
BIT 6 BIT 1
Loaded Last
BIT 0
LOAD/LATCH
LOAD/LATCH
t LLD
t LLW
Next
Clock
Pulse
t LLO
Figure 3: Serial Control Data Loading Diagram
1998 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 910 744 5050 Fax: 910 744 5054
Doc. # 20480077.006
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies