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LT1161CS

Quad Protected High-Side MOSFET Driver

Linear Technology 

LT1161

APPLICATIONS INFORMATION

Drain Sense Configuration

The LT1161 uses supply-referenced current sensing. One

input of each channel’s current-sense comparator is con-

nected to a drain sense pin, while the second input is offset

65mV below the supply bus inside the device. For this

reason, pins 11 and 20 of the LT1161 must be treated not

only as supply pins, but as the reference inputs for the

current-sense comparators.

Figure 4 shows the proper drain sense configuration for

the LT1161. Note that the sense pin goes to the drain end

of the sense resistor, while the two V+ pins are tied to each

other and connected to supply at the same point as the

positive ends of the sense resistors. Local supply

decoupling at the LT1161 is important at high input

voltages (see Protecting Against Supply Transients).

The drain sense threshold voltage has a positive tempera-

ture coefficient, allowing PTC sense resistors to be used

(see Printed Circuit Board Shunts). The selection of RS

should be based on the minimum threshold voltage:

RS

=

50mV

ISET

Thus the 0.02Ω drain sense resistor in Figure 4 would yield

a minimum trip current of 2.5A. This simple configuration

is appropriate for resistive or inductive loads which do not

generate large current transients at turn-on.

Automatic Restart Period

The timing capacitor CT shown in Figure 4 determines the

length of time the power MOSFET is held off following a

current limit trip. Curves are given in the Typical Perfor-

mance Characteristics to show the restart period for

various values of CT. For example, CT = 0.33µF yields a

50ms restart period.

Defeating Automatic Restart

Some applications are required to remain off after a fault

occurs. When the LT1161 is being driven from CMOS

logic, this can be easily implemented by connecting

resistor R1 between the input and timer pins as shown in

Figure 5. R1 supplies the sustaining current for an SCR

which latches the timer pin low. This prevents the MOSFET

gate from turning ON until the input has been recycled.

5V

CMOS

LOGIC

ON = 5V

OFF = 0V

TIMER

R1

LT1161

2k

INPUT

1161 F05

Figure 5. Latch-Off Input Network (Auto-Restart Defeated)

Inductive vs Capacitive Loads

24V

+ 100µF Turning on an inductive load produces a relatively benign

V+

50V

ramp in MOSFET current. However, when an inductive

V+

+

RS

load is turned off, the current stored in the inductor needs

LT1161

10µF

0.02Ω

(PTC)

somewhere to decay. A clamp diode connected directly

DS1

across each inductive load normally serves this purpose.

T1

G1

1161 F04

IRFZ34

If a diode is not employed the LT1161 clamps the MOSFET

CT

GND

1µF

GND

gate 0.7V below ground. This causes the MOSFET to

24V, 2A

resume conduction during the current decay with (V+ +

SOLENOID

VGS + 0.7V) across it, resulting in high dissipation peaks.

Figure 4. Drain Sense Configuration

Capacitive loads exhibit the opposite behavior. Any load

that includes a decoupling capacitor will generate a cur-

rent equal to CLOAD × (∂V/∂t) during capacitor in-rush.

With large electrolytic capacitors, the resulting current

6

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