VSC7185TW 查看數據表（PDF） - Vitesse Semiconductor

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VSC7185TW

Quad Transceiver for Gigabit Ethernet and Fibre Channel

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7185

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Pin

D1, D2

E3, E4

C1

A6, B6

C6, D6

A7

B11, A12

B12, C12

D12

C17, D14

D15, D16

D17

E1

E2

A5

B5

C10

D10

B16

B17

U4, U3

U7, U6

U11, U10

U14, U13

N14

C9

R17

F2

A4

B10

B15

P9

R9

Name

RX00, RX01

RX02, RX03

RX04

RX10, RX11

RX12, RX13

RX14

RX20, RX21

RX22, RX23

RX24

RX30, RX31

RX32, RX33

RX34

RC00

RC01

RC10

RC11

RC20

RC21

RC30

RC31

SI0+, SI0-

SI1+, SI1-

SI2+, SI2-

SI3+, SI3-

PLUP

SLPN

SYNC

SYN0

SYN1

SYN2

SYN3

CAP0

CAP1

Description

OUTPUT - SSTL-2: 5-Bit Receive Bus for Channel 0. Parallel data on this bus is

synchronous to RC00 and RC01. RX00 is the first bit received.

OUTPUT - SSTL-2: 5-Bit Receive Bus for Channel 1. Parallel data on this bus is

synchronous to RC10 and RC11. RX10 is the first bit received.

OUTPUT - SSTL-2: 5-Bit Receive Bus for Channel 2. Parallel data on this bus is

synchronous to RC20 and RC21. RX20 is the first bit received.

OUTPUT - SSTL-2: 5-bit Receive bus for Channel 3. Parallel data on this bus is

synchronous to RC30 and RC31. RX30 is the first bit received.

OUTPUT - SSTL-2: Recovered complementary clocks for Channel 0 at

1/10th the incoming baud rate. Synchronous to RX0(0:4) and SYN0.

OUTPUT - SSTL-2: Recovered complementary clocks for Channel 1 at

1/10th the incoming baud rate. Synchronous to RX1(0:4) and SYN1.

OUTPUT - SSTL-2: Recovered complementary clocks for Channel 2 at

1/10th the incoming baud rate. Synchronous to RX2(0:4) and SYN2.

OUTPUT - SSTL-2: Recovered complementary clocks for Channel 3 at

1/10th the incoming baud rate. Synchronous to RX3(0:4) and SYN3.

INPUT - Differential PECL (AC-Coupling recommended): Serial receive data inputs

for Channel x which are selected when PLUP is LOW. [Internally biased to VCC/2]

INPUT - SSTL-2: Parallel Loopback Enable input. SIi is input to the CRU for Channel

x (normal operation) when PLUP is LOW. When HIGH, internal loopback paths from

SOi to SIi are enabled. Refer to Table 1.

INPUT - SSTL-2: Serial Loopback Enable Input. Normal operation when HIGH.

When LOW, SIi is looped back to SOi internally for diagnostic purposes. Refer to

Table 1 and related description.

INPUT - SSTL-2: Enables SYNi and Word Alignment when HIGH. When LOW,

keeps current word alignment and disables SYNi (always LOW).

OUTPUT - SSTL-2: Comma Detect for Channel i. This output goes HIGH for both

half-characters to indicate that a comma character (‘0011111XXX’) has been detected.

SYNi is enabled when SYNC is HIGH.

ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically

0.1µF connected between CAP0 and CAP1. Amplitude is less than 3.3V.

G52324-0, Rev. 3.0

8/28/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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