AD1843 查看數據表（PDF） - Analog Devices
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AD1843 Datasheet PDF : 64 Pages
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AD1843
PIN CONFIGURATIONS
100-Lead TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SDO 1
SDFS 2
NC 3
GNDD 4
VDD 5
TSI 6
TSO 7
NC 8
GNDD 9
VDD 10
CS 11
BM 12
NC 13
NC 14
AUX3R 15
AUX3L 16
AUX2R 17
AUX2L 18
AUX1R 19
AUX1L 20
MICL 21
MICR 22
MIN 23
NC 24
VCC 25
AD1843
TOP VIEW
(Not to Scale)
75 GNDD
74 XCTL1
73 NC
72 XCTL0
71 SYNC3
70 SYNC2
69 SYNC1
68 NC
67 GNDD
66 VDD
65 RESET
64 PWRDWN
63 NC
62 VDD
61 PDMNFT
60 NC
59 GNDA
58 HPOUTL
57 HPOUTC
56 HPOUTR
55 VCC
54 SUML
53 SUMR
52 NC
51 VCC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Serial Interface (Continued)
Pin Name PQFP TQFP
CS
9
11
TSO
6
7
TSI
5
6
XCTL[1:0] 59, 58
72, 74
I/O Description
I
Chip Select. When CS is set HI, the serial interface I/O pins will be in their normal
active states. When CS is reset LO, SCLK, SDFS, and SDO are three-
stated; SCLK, SDFS and SDI inputs are ignored; and TSO drives out the logic
level received on TSI.
O Time Slot Output. TSO is asserted HI by the AD1843 simultaneously with the LSB
of the last time slot used by the AD1843. It is used to daisy-chain multiple AD1843s
on a common TDM serial bus. If the power-down (PWRDWN) pin is asserted or if
the chip select pin (CS) is deasserted, TSO is set to the logic level on the TSI pin,
allowing powered-down or unselected AD1843s on a daisy-chain to be skipped.
I
Time Slot Input. Asserting TSI HI indicates to the AD1843 that it should use
the next six time slots beginning on the next SCLK period. It also enables TSO
to be asserted at the end of these six time slots. TSI is ignored (but should be tied
LO) when the AD1843 is the bus master since the bus master uses the first time
slots in a TDM frame.
I/O External Control. These signals reflect the status of bits (Data 8 and 9) in Control
Register Address 28 of the AD1843. They may be used for signaling or controlling
external logic.
–8–
REV. 0
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