AD1843 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD1843 Datasheet PDF : 64 Pages
| |||
Analog Signals
Pin Name PQFP
LINLP
28
LINLN
29
LINRP
26
LINRN
27
MICL
18
TQFP
35
36
33
34
21
MICR
17
22
AUX1L
16
AUX1R
15
AUX2L
14
AUX2R
13
AUX3L
12
AUX3R
11
MIN
19
MOUT
35
LOUT1L
36
LOUT1R
34
HPOUTL 47
HPOUTC 46
HPOUTR 45
LOUT2LP 32
LOUT2LN 33
LOUT2RP 30
LOUT2RN 31
SUML
43
SUMR
42
Clocks
Pin Name PQFP
CLKOUT 76
20
19
18
17
16
15
23
44
45
43
58
57
56
40
41
38
39
54
53
TQFP
95
SYNC[3:1] 57, 56, 55 71, 70, 69
CONV[3:1] 75, 71, 67 94, 89, 84
BIT[3:1] 74, 70, 66 92, 87, 82
AD1843
I/O Description
I
Line Input Left Channel Positive Differential Signal.
I
Line Input Left Channel Negative Differential Signal.
I
Line Input Right Channel Positive Differential Signal.
I
Line Input Right Channel Negative Differential Signal.
I
Microphone Input Left Channel. Microphone input for the left channel. This
signal can be either line level or –20 dB from line level.
I
Microphone Input Right Channel. Microphone input for the right channel.
This signal can be either line level or –20 dB from line level.
I
Auxiliary #1 Left Channel Line Input.
I
Auxiliary #1 Right Channel Line Input.
I
Auxiliary #2 Left Channel Line Input.
I
Auxiliary #2 Right Channel Line Input.
I
Auxiliary #3 Left Channel Line Input.
I
Auxiliary #3 Right Channel Line Input.
I
Monaural (Mono) Line Input.
O Monaural (Mono) Line Output.
O Line Output #1 Left Channel.
O Line Output #1 Right Channel.
O Headphone Output Left Channel.
Headphone Common Return.
O Headphone Output Right Channel.
O Line Output #2 Left Channel Positive Differential Signal.
O Line Output #2 Left Channel Negative Differential Signal.
O Line Output #2 Right Channel Positive Differential Signal.
O Line Output #2 Right Channel Negative Differential Signal.
I
Mixer Line Input Left Channel.
I
Mixer Line Input Right Channel.
I/O Description
O Clock Output. This signal is a buffered version of XTALO (with a duty cycle
restored to at least 60%/40%), the crystal clock output. This pin is enabled by
default but can be three-stated by programming a bit in Control Register
Address 28. The CLKOUT frequency is 24.576 MHz.
I Sync Inputs. These SYNC signals are used as the clock source inputs to three
receptive PLLs in the AD1843. These pins accept a clock at, or at a multiple of,
the desired sample rate for A-to-D and D-to-A conversions. These inputs are
ignored if a sample rate is programmed directly, but should never be left floating.
O Conversion Clock Outputs. These output clocks have an average period equal to (or 128
times) the internal sample rates of the AD1843. These clock outputs are three-stated
by default but can be enabled by programming bits in Control Register Address 28.
O Bit Clock Outputs. These output clocks can be individually programmed to
multiples of the sample rates. Support for V.34 or V.32 bit rates is available.
These clock outputs are three-stated by default but can be enabled by
programming bits in Control Register Address 28.
REV. 0
–9–
Share Link: 