HS-80C86RH(1995) 查看數據表（PDF） - Intersil
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HS-80C86RH Datasheet PDF : 37 Pages
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HS-80C86RH
Waveforms (Continued)
T1
CLK
S2, S1, S0 (EXCEPT HALT)
TCHSV
WRITE CYCLE
AD15-AD0
TCLAV
82C88
OUTPUTS
SEE NOTES
5, 6
DEN
AMWC OR AIOWC
TCLDV
TCLAX
TCVNV
TCLML
MWTC OR IOWC
T2
T3 TW
T4
TCLSH
(SEE NOTE 8)
TCLDX2
TCLMH
TCLML
TCVNX
TCLMH
INTA CYCLE
AD15-AD0
(SEE NOTES 3, 4)
TCLAZ
AD15-AD0
TSVMCH
RESERVED FOR
CASCADE ADDR
TCLMCL
TDVCL
POINTER
TCLDX1
MCE/PDEN
TCLMCH
DT/R
82C88 OUTPUTS
SEE NOTES 5, 6
INTA
TCHDTL
TCLML
TCHDTH
TCVNV
TCLMH
DEN
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD15-AD0
TCLAV
INVALID ADDRESS
S2
TCVNX
TCHSV
TCLSH
FIGURE 10. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88)
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer ad-
dress is shown for the second INTA cycle.
5. Signals at HS-82C85RH or 82C88 are shown for reference only.
6. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active
high 82C88 CEN.
7. All timing measurements are made at 1.5V unless otherwise noted.
8. Status inactive in state just prior to T4.
Spec Number 518055
878
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