ADM1024ARUZ-REEL7 查看數據表（PDF） - Analog Devices

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ADM1024ARUZ-REEL7

System Hardware Monitor with Remote Diode Thermal Sensing

Analog Devices 

THERM INPUT/OUTPUT

The Thermal Management Input/Output (THERM) is a logic

input/output with an internal, 100 kΩ pull-up resistor, that

provides a separate output for temperature interrupts only. It is

enabled by setting Bit 2 of Configuration Register 1. The THERM

output has two operating modes that can be programmed by

Bit 3 of Configuration Register 2 (address 4Ah). With this bit

set to the default value of 0, the THERM output operates in

“Default” interrupt mode. With this bit set to 1, the THERM

output operates in “ACPI” mode.

Thermal interrupts can still be generated at the INT output while

THERM is enabled, but if these are not required they can be

masked by writing a 1 to Bit 0 of Configuration Register 2

(address 4Ah). The THERM pin can also function as a logic

input for an external sensor, for example, a temperature sensor

such as the ADM22105 used in Figure 16b. If THERM is

taken low by an external source, the analog output will be

forced to FFh to switch a controlled fan to maximum speed.

This also generates an INT output as previously described.

DEFAULT MODE

In Default mode, the THERM output operates like a thermo-

stat with hysteresis. THERM will go low and Bit 5 of Interrupt

Status Register 2 will be set, if the temperature measured by any

of the sensors exceeds the high limit programmed for that

sensor. It will remain asserted until reset by reading Interrupt

Status Register 2, by setting Bit 6 of Configuration Register 1,

or when the temperature falls below the low limit programmed

for that sensor.

TEMP

HIGH LIMIT

TEMP

LOW LIMIT

TEMP

THERM

ANALOG

OUTPUT

CLEARED BY CLEARED BY

PROGRAMMED READ OR TEMP FALLING

VALUE

THERM CLEAR BELOW LOW

LIMIT

FFH

EXT

THERM

INPUT

Figure 16a. INT or THERM Output in Default Mode

If THERM is cleared by reading the status register, it will be

reasserted after the next temperature reading and comparison if

it remains above the high limit.

If THERM is cleared by setting Bit 6 of Configuration Register

1, it cannot be reasserted until this bit is cleared.

THERM will also be asserted if one of the hardware temperature

limits at addresses 13h, 14h, 17h, or 18h is exceeded for three

consecutive measurements. When this happens, the analog

output will be forced to FFh to boost a controlled cooling fan

to full speed.

ADM1024

Reading Status Register 1 will not clear THERM in this case,

because errors caused by exceeding the hardware temperature

limits are stored in a separate register that is not cleared by

reading the status register. In this case, THERM can only be

cleared by setting Bit 0 of Configuration Register 2.

THERM will be cleared automatically if the temperature falls at

least 5 degrees below the limit for three consecutive measurements.

ACPI MODE

In ACPI mode, THERM responds only to the hardware tem-

perature limits at addresses 13h, 14h, 17h, and 18h, not to the

software programmed limits.

HARDWARE

TRIP POINT

5؇

TEMP

THERM

PROGRAMMED

ANALOG

VALUE

FFh

OUTPUT

EXT

FFh

THERM

INPUT

Figure 16b. THERM Output in ACPI Mode

THERM will go low if either the internal or external hardware

temperature limit is exceeded for three consecutive measurements.

It will remain low until the temperature falls at least 5 degrees

below the limit for three consecutive measurements. While

THERM is low, the analog output will go to FFh to boost a

controlled fan to full speed.

RESET INPUT/OUTPUT

RESET (Pin 12) is an I/O pin that can function as an open-drain

output, providing a low going 20 ms output pulse when Bit 4 of

the Configuration Register is set to 1, provided the reset func-

tion has first been enabled by setting Bit 7 of Interrupt Mask

Registers 2 to 1. The bit is automatically cleared when the reset

pulse is output. Pin 11 can also function as a RESET input by

pulling this pin low to reset the internal registers of the ADM1024

to default values. Only those registers that have power-on default

values as listed in Table VII are affected by this function.

The DAC, Value, and Limit Registers are not affected.

NAND TESTS

A NAND gate is provided in the ADM1024 for Automated Test

Equipment (ATE) board level connectivity testing. The device

is placed into NAND Test Mode by powering up with Pin 11

held high. This pin is automatically sampled after power-up; if it

is connected high, then the NAND test mode is invoked.

In NAND test mode, all digital inputs may be tested as illustrated

below. NTEST_OUT/ADD will become the NAND test output

pin. To perform a NAND tree test, all pins included in the NAND

tree should first be driven high. Each pin can then be toggled

and a resulting toggle can be observed on NTEST_OUT/ADD.

REV. B

–21–

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