AD725 查看數據表（PDF） - Analog Devices

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AD725

Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port

Analog Devices 

AD725

HSYNC/VSYNC

(USER INPUTS)

RIN/GIN BIN

(USER INPUTS)

MODULATOR

RESTORE

INPUT

CLAMPS

BURST FLAG/

DELAY LINE RESET

LUMA

CRMA

tSW

tSM

tMW

tSR

tSD

tSS

tSC

tSB

tRW

tDW

tBY

tBC

Figure 18. Timing Diagram (Not to Scale)

Table I. Timing Description (See Figure 18)

Symbol

tSW

tSB

tSM

tMW

tSR

tRW

tSD

tDW

tSS

tBY

tSC

tBC

Name

Sync Width

Sync to Blanking

End

Sync to Modulator

Restore

Modulator Restore

Width

Sync to RGB DC

Restore

DC Restore Width

Sync to Delay Line

Reset

Delay Line Reset

Width

Sync Input to Luma

Sync Output

Blanking End to

LUMA Start

Sync to Colorburst

Blanking End to

CRMA Start

Description

Input valid sync width for burst

insertion (user-controlled).

Minimum sync to color delay

(user-controlled).

Delay to modulator clamp start.

Length of modulator offset clamp

(no chroma during this period).

Delay to input clamping start.

Length of input clamp (no RGB

response during this period).

Delay to start of delay line

clock reset.

Length of delay line clock reset

(no luma response during this

period), also burst gate.

Delay from sync input assertion

to sync in LUMA output.

Delay from RGB input assertion

to LUMA output response.

Delay from valid horizontal sync

start to CRMA colorburst output.

Delay from RGB input assertion

to CRMA output response.

NTSC1

Min

2.8 µs

Max

5.3 µs

Min

8.2 µs

392 ns

140 ns

5.4 µs

2.5 µs

5.7 µs

2.5 µs

typ

310 ns

typ

340 ns

typ

5.8 µs

typ

360 ns

NOTES

1Input clock = 14.318180 MHz, STND pin = logic high.

2Input cock = 17.734475 MHz, STND pin = logic low.

PAL2

Min

3.3 µs

Max

5.4 µs

Min

8.1 µs

298 ns

113 ns

5.6 µs

2.3 µs

5.8 µs

2.3 µs

typ

265 ns

typ

280 ns

typ

5.9 µs

typ

300 ns

–10–

REV. 0

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