EDS1232AABB 查看數據表（PDF） - Elpida Memory, Inc

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EDS1232AABB

128M bits SDRAM

Elpida Memory, Inc 

EDS1232AABB, EDS1232AATA

Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)

After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the

Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are

performed internally, so there is no need for external control. Before executing self refresh, all banks must be

precharged.

CLK

CKE

/CS

/RAS

/CAS

/WE

BA0, BA1

(Bank select)

A10

Add

Self Refresh Entry Command

Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)

This command can stop the current burst operation.

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0, BA1

(Bank select)

A10

Add

Burst Stop Command in Full Page Mode

No operation (/CS = Low, /RAS, /CAS, /WE = High)

This command is not an execution command. No operations begin or terminate by this command.

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0, BA1

(Bank select)

A10

Add

No Operation

Preliminary Data Sheet E0205E50 (Ver. 5.0)

15

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