NT5DS16M8AW-66 查看數據表（PDF） - Nanya Technology

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NT5DS16M8AW-66

128Mb DDR333/300 SDRAM

Nanya Technology 

NT5DS32M4AT NT5DS32M4AW

NT5DS16M8AT NT5DS16M8AW

128Mb DDR333/300 SDRAM

AC Input Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

Characteristics)

Symbol

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

Parameter/Condition

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals

Input Differential Voltage, CK and CK Inputs

Input Crossing Point Voltage, CK and CK Inputs

Min

Max

Unit

VREF + 0.31

V

VREF − 0.31

V

0.62

VDDQ + 0.6

V

0.5*VDDQ − 0.2 0.5*VDDQ + 0.2 V

Notes

1, 2

1, 2

1, 2, 3

1, 2, 4

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until VREF stabilizes.

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

Characteristics)

Symbol

Parameter/Condition

DDR333 DDR300

tCK=6ns tCK=6.6ns Unit

Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and

IDD0

DQS inputs changing twice per clock cycle; address and control inputs changing

85

mA

once per clock cycle

Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC

IDD1

(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock

110

mA

cycle

IDD2P

Precharge Power-Down Standby Current: all banks idle; power-down mode;

CKE ≤ VIL (max)

15

mA

IDD2N

Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);

address and control inputs changing once per clock cycle

35

mA

IDD3P

Active Power-Down Standby Current: one bank active; power-down mode;

CKE ≤ VIL (max)

15

mA

Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);

IDD3N CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per

60

mA

clock cycle; address and control inputs changing once per clock cycle

Operating Current: one bank; Burst = 2; reads; continuous burst; address and

IDD4R

control inputs changing once per clock cycle; DQ and DQS outputs changing

twice per clock cycle; CL = 2.5; IOUT = 0mA

165

mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and

IDD4W control inputs changing once per clock cycle; DQ and DQS inputs changing twice

150

mA

per clock cycle; CL = 2.5

IDD5

Auto-Refresh Current: tRC = tRFC (min)

IDD6

Self-Refresh Current: CKE ≤ 0.2V

Operating current: four bank; four bank interleaving with BL = 4, address and

IDD7

control inputs randomly changing; 50% of data changing at every transfer;

t RC = t RC (min); I OUT = 0mA.

170

mA

3

mA

150

mA

Notes

1

1

1

1

1

1

1

1

1

1, 2

1

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

Preliminary

08/01

21

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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