SL1714CKG 查看數據表（PDF） - Mitel Networks

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SL1714CKG

Quadrature Downconverter

Mitel Networks 

SL1714

I & Q baseband outputs

The SL1714 offers a greatly improved drive capability over

the SL1710 and as such is much less sensitive to the load

conditions.

It is still important however to carefully balance the loads

presented to the SL1714 to ensure no differential gain or

phase degradation is introduced by the load circuits, which will

also include effects due to track striplines etc.

For demonstration purposes the output is unsuitable for

connection via co-axial cables to standard test equipment,

where such equipment is normally 50 Ω or highly capacitive.

To overcome this problem the outputs of the SL1714 are

therefore buffered through emitter followers which are

optimised to drive 50 Ω loads without appreciable degradation

in the SL1714 performance. These buffer stages are

selectable so enabling the outputs to be loaded directly for

interfacing direct with an ADC via a low capacitive link.

In most applications the SL1714 will normally interface

direct into the ADC converter such as the VP216, which will

present a >1 KΩ low capacitive load.

The output is optimised for typical drive levels of 760

mVp-p and the onset of clipping is typically > 1.5V p-p.

SL1714 Evaluation Board

This board has been created to show the operation of the

SL1714 I/Q downconverter.

It does not attempt to simulate a real system, since in

practice the 479.5MHz IF oscillator on the SL1714 (and the

60MHz clock on the subsequent ADC) would be controlled via

the baseband IQ demodulator chip such as the VP305 which

follows the dual channel ADC. For simplicity, the VCO is

locked using GPS SP5611 synthesiser, controlled via an I2C

bus.

For full evaluation, 30V and 5V supplies are necessary.

Supplies

The board must be provided with the following supplies:

A) 5V for the SL1714 and SP5611 and 30V for the

varactor line.

The supply connector is a 3 pin 0.1" pitch pin header. The

centre pin of the connector is GND.

Outputs driven into hard clipping can exhibit amplitude

decline. AGC loops should be designed to take account of this.

I2C Bus connections

The board is provided with an RJ11 I2C bus connector

which feeds directly to the SP5611 synthesiser.

This connects to a standard 6-way connector cable which

is supplied with the I2C/3-wire bus interface box.

Input and Output connections

The board is provided with the following connectors:

A) IF I/P SMA connector SK1which is AC coupled to the

RF input of the SL1714.

B) I CH OUT SK2 and Q CH OUT SK3 which provide

either a buffered or direct baseband output signal from

the SL1714 (depending on which way the links LK1

and LK2 are set). The output buffers should be used

when driving 50Ω test equipment or co-axial lines.

Links and Switches

The board is provided with the following:

VCO DISABLE switch

This disables the VCO of the SL1714. It does NOT power

down the chip.

AGC ADJUST potentiometer

The potentiometer sets the AGC input voltage of the

SL1714 which controls the gain of the chip. TP1 is provided as

a means of monitoring the AGC voltage.

LK1 and LK2

These are links which may be placed either vertically or

horizontally to connect the outputs of the SL1714 either

directly or via buffers to the SMA output connectors of the

board.

If the links are placed vertically 1-2 and 3-4 the outputs are

connected directly.

If the links are placed horizontally 1-3 and 2-4 the ouputs

are connected via buffers.

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