L6000 查看數據表（PDF） - STMicroelectronics

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L6000

SINGLE CHIP READ & WRITE CHANNEL

STMicroelectronics 

MODE CONTROL(continued)

PWRDN Mode

Register bits

L6000

DESCRIPTION

X X X 1 1 1 0 1 1 TEST FILTER MODE : All major blocks except the Active

Filter with Boost and Differentiator are powered down via

Register ( R02 ).

0 1 1 1 1 1 1 0 0 TEST DATA SEPARATOR READ MODE : Only the Data

Separator and Frequency Synthesizer are on, and the pin

READ DATA I/O is a test input.

1 0 1 1 1 1 1 0 0 TEST DATA SEPARATOR WRITE MODE : Only the Data

Separator Write circuitry and the Frequency Synthesizer are

on, for testing this specific circuitry.

X X X 1 1 1 1 0 0 TEST FREQUENCY SYNTHESIZER MODE: The front end is

powered down. The Frequency Synthesizer is powered on for

testing.

CIRCUIT OPERATION

General

The L6000 is a state of the art integrated read

channel. The major functional blocks are :

1) Pulse Detector and Servo Demodulator, with

dual servo burst measurement channels and

2 different qualification schemes for data.

2) Tunable Active equiripple filter with tunable

Pulse slimming Boost and Active Differentia-

tor.

3) (1, 7) RLL Combined Data Separator and

ENDEC with active window centering and

margin shifting from external commands.

4) A (M+1) divide by (N+1) Frequency synthe-

sizer, using an external reference, and with 7

bits of DAC control accuracy.

5) A high speed serial interface controlling most

functions and adjustement.

The L6000 is designed to be used with data rates

as high as 32 Mbits/sec. Selection of a different

recording density is done by setting new divisors

in the Frequency Synthesizer via serial registers.

Power Management

The serial interface should load all appropriate

control registers as soon as Power on Reset

clears in the system. This prevents spurious con-

ditions in all the affected blocks. After the regis-

ters are written, then the appropriate Power down

modes can be used. The power management of

the L6000 is under the control of the PWRDN

MODE pin and the Power Down Control Register

(R02). The following table defines the power

down modes and register bits controlling them:

Bit Symbol

Function

0

PD Pulse Detector Power Down

1

SD Servo Demodulator Power Down

2 FLTR Filter Power down

3

DS Data Separator Power Down

4

FS Frequency Synthesizer Power Down

5-7

Bits 5-7 are Hard-Coded to 111.

When the PWRDN MODE pin is asserted it pow-

ers down ALL functions with the exception of the

serial port, which remains active in ALL power

down modes. When the PWRDN MODE pin is

deasserted, each individual major function block

can be powered on or OFF separately from the

serial port PD register. This feature is useful for

sophisticated power saving state machines in

systems. Toggling the bit in the register is the

only necessary condition to turn on or OFF a ma-

jor block; PWRDN MODE does not have to be cy-

cled for each separate register load.

Serial Interface

The serial interface consists of the 3 signals SE-

RIAL ENABLE, SERIAL CLOCK and SERIAL

DATA I/O. The first two signals are inputs which

are always powered on and active. SERIAL

DATA I/O is a bidirectional pin which becomes an

ouput on a register read. A value can be put into

the L6000 (register WRITE) or a value can be in-

terrogated from the L6000 (register READ). The

bottom half of the diagram is a register READ

where a value is interrogated from the L6000. To

do either operation, SERIAL DATA ENABLE is

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