L6000 查看數據表（PDF） - STMicroelectronics

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L6000

SINGLE CHIP READ & WRITE CHANNEL

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WRITE operation format is the following. The first

bit is LOW, meaning write, followed by the 7bit

register address, LSB first. The last 8 bits then

are the data to be written to the register, also LSB

first. During this to entire operation, SERIAL

DATA I/O is an active input. The READ operation

format is the following. The first bit now is HIGH,

meaning read, and that is followed by the 7bit

register address, LSB first. Upon receipt of the

last bit of address, the pin SERIAL DATA I/O

turns and becomes an active output, and outputs

the 8 bits stored in the addressed register, LSB

first on the following 8 SERIAL CLOCK+s.

Pulse Detector and Servo Demodulator

The purpose of the Pulse Detector is to qualify

and detect the position of flux transitions written

on the disk. The first stage of the Pulse Detector

is the AGC amplifier. It is a wideband, differential

amplifier which characteristic (Gain vs. Voltage) is

positive slope and linear in DB and thermal com-

pensated. The amplifier inputs have a low-imped-

ance state where the inputs are shorted by a FET

switch during modes where transients are likely to

occur. The amplifier gain is controlled by 2 ca-

pacitors connected to to the DATA BYP and

SERVO BYP pins. The capacitor which controls

the gain is selected by the SERVO GATE signal,

asserted meaning Servo. In modes where the

AGC is powered on, the selected capacitor will be

charged from a dual rate charge pump. When the

individual signals HOLD DATA AGC and HOLD

SERVO AGC are asserted, the respective capaci-

tors are disconnected from the charge pumps, but

they remain in control of the AGC gain. If a fixed

gain is desired, a voltage divider can be con-

nected to either DATA BYP or SERVO BYP pin.

In order to minimize the time required to restore

the correct AGC output amplitude, the input

switching to unshorted inputs and the AGC at-

tack/delay currents are under timed, state control.

The time to restore the inputs and AGC to normal

operation is set to 1 usec. However, the AGC at-

tack is controlled by amplitude and may take

longer to settle. The nominal AGC attack (dis-

charge) current is set to 0.18 mA but is increased

to 1.3 mA when the AGC amplitude exceedes

1.25 times its set point. The nominal AGC decay

current is increased from 0.004 mA to 0.080 mA

in the recovery fast/decay mode. The high decay

current of 80uA is only on for the second micro-

second after the mode switch initiates the AGC

reacquisition. Note that the fast Decay current is

available in the recovery mode, while any ampli-

tude transient over the threshold will activate the

fast Attack current.

The modes where the inputs go from shorted to

unshorted are :

1) From Full Power Down either Servo mode

(SERVO GATE active)

2) From Full Power Down to Idle mode.

L6000

3) From Full Power Down to Read mode.

4) From Write to Read mode.

5) From Write to Idle mode.

The modes where the inputs go from unshorted

to shorted are : 1) From Read to Write mode. 2)

From any mode to Full Power Down mode.

The modes where the fast attack and decay cur-

rents become active are :

1) From Full Power Down to Idle mode.

2) From Full Power Down to Read mode.

3) From Write to Read mode.

Nominally the AGC amplifier outputs will be AC

coupled to the Active Filter outputs and then the

Active Filter outputs, both Normal and Differential

will be AC coupled back to the Pulse Detector

block.

Pulse Detector

This block has 4 inputs, 2 fully differential pairs.

The CLOCK PATH inputs are a zero crossing de-

tector, zero crossing assumed to occur at the am-

plitude peaks of the pulses. This input pairs shall

be connected to the Active Filter differentiator.

The DATA PATH inputs are amplitude ( threshold

) qualifiers and are to be connected to the Active

Filter normal outputs. Call factory for schematic

for the recommended connection in the system.

Dual threshold comparators are available in the

Pulse Detector. If the DEDC bit is set in the

DataVth register ( ROA ), then separate compari-

sons are done on negative and positive peaks. If

the bit is reset, then the polarity of the next pulse

to be qualified must be opposite of the last. This

check can lead to a 2 bit missing error for just 1

pulse under threshold. The threshold used for

comparison is set in the two threshold register

DataVth and ServoVth. These register feed the

threshold DAC (VTHDAC) which developes the

actual floating hysteresis level and thresholds

from the input LEVEL (a bufferred signal rectified

from the filter normal outputs. The hysteresis is

always a percentage, of 0.7 the peak to peak

swing at DATA PATH inputs, and is accurate from

10 to 80 % with a 1 % accuracy. The floating hys-

teresis generator also has a time constant which

is developed from the components connected to

SERVO TC RES, DATA TC RES, LEVEL, and

LEVEL REF V. This time constant is, in effect, a

time domain filter implemented in the qualifier

channel that has the purpose to realize an enve-

lope detector on the rectified signal feeding the

DATA PATH inputs. The two constant is changed

depending on SERVO GATE state.. Recom-

mended values for Rext on SERVO TC RES and

DATA TC RES is TBD ; for Cext on LEVEL and

LEVEL REF V it is TBD. The output of the Pulse

Detector block is READ DATA I/O, and this pin is

active ONLY in the Idle and Servo modes. It is an

approximately 24 nsec negative going TTL com-

17/24

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