L6000 查看數據表（PDF） - STMicroelectronics

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L6000

SINGLE CHIP READ & WRITE CHANNEL

STMicroelectronics 

L6000

1.7 RLL ENCODING

Previuos RLL

Code Word

Last Bits

NRZ Data Bits

Present Next

RLL

Code Bits

X

0

100X101

X

0

101X110

X

0

1100010

X

0

11* *100

1

0

000X001

1

0

001X000

0

0

010X001

0

0

011X000

X

1

000X001

X

1

001X010

X

1

0100010

X

1

01* *000

Y2’

Y3 D1 D2 D3 D4 Y1 Y2 Y3

X = Do Not Care

* = Not All Zeros

1, 7 RLL CODE SET

Read Mode

The phase comparator enters its phase only com-

pare mode after three cycles of a 3T pattern. This

means that the leading edge of READ DATA

arms the comparator and then the phase com-

parison is done between the trailing edge of

READ DATA and the rising edge of the closest

VCO cycle. The time between the two READ

DATA edges is 1 VCO cycle, or 1/3 bit cell and is

generated by an internal one-shot and the PLL

Control DAC.

The Window Shift function of the L6000 is pro-

vided for testing purposes, and advanced recov-

ery from read errors. To shift the bit position from

its nominal centerd position in the decode win-

dow, a value is written to the WinShift register via

the serial interface. The shift value will take effect

after SERIAL ENABLE is deasserted. The direc-

tion is determined by the Direction bit in the regis-

ter. See the Register Definition section for the

complete set of values and their effect. To do the

Window shift function, the WinShift register sets a

current in the WS DAC wich than adds or sub-

tracts current in the 1/2 VCO cycle delay for the

Data Synchronizer. This then changes the posi-

tion of the trailing edge of the READ DATA pulse

at the Synchronizer ONLY. Since the edge posi-

tion doesn’t change relative to the VCO at the

phase lock is unaffected, and only the bit position

is moved inside the decode window in the Syn-

chronizer.

The VCO has a zero phase restart feature which

allows for very quick acquisition of the READ

DATA phase being recovered from the disk. The

VCO is kept at frequency Fout during Idle mode,

and when Preamble is detected, the zero phase

restart first turn OFF the VCO, then restarts it in

phase with the first received data bit.

20/24

ABOVE VOLTAGE MONITOR

The above voltage bit is used to actively center

the bit in the window by trimming the operating

current of PLL Control DAC to its midpoint of op-

eration.

To optimize this time from temperature and proc-

ess variations, the Above Voltage check should

be performed on a periodic (at least every fre-

quency switch) basis. This will center the operat-

ing point of the VCO and set the 1/2 VCO cycle

delay closet to nominal.

Above Voltage monitor bit (Register 4, B7):

This feature allows the drive microprocessor to

set the VCO to the center of its capture range,

and to remove any offset error from the delay

one-shots in the Data Separator. By changing the

setting of the VCO center register (04), the drive

microprocessor caN maxime the loop lock range

(and minimize margin timing error at power up).

The comparator driving this bit allows for setting

the VCO DAC (Register 04) to place the Data

Separator VFO to its mid-point of operation. It is

intended for use a power-up time calibration, but

can be done at any time power is applied to the

L6000. The microprocessor which loads the regis-

ter values monitors this bit in the following algo-

rithm:

1.Set the Numerator and Denominator values

for the first data rate in Register 0E and 06,

respectively.

2. Write the nominal value chosen to the VCO,

DAC, Register 04.

3.Read the Above Voltage bit: if it is HIGH, de-

crease the value in Register 04 by 1. If it is

LOW, increase the value in Register 04 by 1.

4.Read the bit again; if it has reversed polarity

store the value written to Register 04 as the

Calibrated VCO DAC Register 2 value for fu-

ture use when in that zone. If it has not, re-

peat step 3.

5.Repeat the same procedure (steps 1 to 4) for

all zones and store the Calibrated Register 2

values for future use.

Soft Sector - Read Back

The assertion of READ GATE initiates the lock up

sequence. The lock up sequence proceedes as

follows:

1.An Address Mark is searched for. The Ad-

dress Mark consists of two sets of 7 0s, 1, 11

0s, 1, 11 0s, 1. When the L6000 detects 6 0s,

then detects 9 0s, TWICE, it generates the

Address Mark found condition, and asserts

ADDR MARK DET. ADDR MARK DET will re-

main asserted until the end of the Read op-

eration. If the 9 0s are not detected within 5

data bits of the 6 0s field, the circuit will auto-

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