M38200E6DXXXFS 查看數據表（PDF） - Renesas Electronics

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M38200E6DXXXFS

Single-chip 8-bit CMOS microcfomputer. PROM 32768 bytes, RAM 1024 bytes. EPROM version

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt request

Fig. 8 Interrupt control

7

0 Interrupt edge selection register

(INTEDGE : address 003A16)

INT0 interrupt edge selection bit

INT1 interrupt edge selection bit

INT2 interrupt edge selection bit

INT3 interrupt edge selection bit

Not used (return “0” when read)

0 : Falling edge active

1 : Rising edge active

7

0 Interrupt request register 1

7

0 Interrupt request register 2

(IREQ1 : address 003C16)

(IREQ2 : address 003D16)

INT0 interrupt request bit

INT1 interrupt request bit

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

CNTR0 interrupt request bit

CNTR1 interrupt request bit

Timer 1 interrupt request bit

INT2 interrupt request bit

INT3 interrupt request bit

Key input interrupt request bit

Serial I/O2 interrupt request bit

Not used (returns “0” when read)

0 : No interrupt request issued

1 : Interrupt request issued

7

0 Interrupt control register 1

7

0 Interrupt control register 2

(ICON1 : address 003E16)

0

(ICON2 : address 003F16)

INT0 interrupt enable bit

INT1 interrupt enable bit

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

CNTR0 interrupt enable bit

CNTR1 interrupt enable bit

Timer 1 interrupt enable bit

INT2 interrupt enable bit

INT3 interrupt enable bit

Key input interrupt enable bit

Serial I/O2 interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

Fig. 9 Structure of interrupt-related registers

19

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