M38072M5-XXXFP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M38072M5-XXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3807 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timers

The 3807 group has seven timers : four 16-bit timers (Timer X, Timer

Y, Timer A, and Timer B) and three 8-bit timers (Timer 1, Timer 2,

and Timer 3).

All timers are down-counters. When the timer reaches either "0016"

or "000016", an underflow occurs with the next count pulse. Then the

contents of the timer latch is reloaded into the timer and the timer

continues down-counting. When a timer underflows, the interrupt

request bit corresponding to that timer is set to "1."

Read and write operation on 16-bit timer must be performed for both

high- and low-order bytes. When reading a 16-bit timer, read from

the high-order byte first. When writing to 16-bit timer, write to the low-

order byte first. The 16-bit timer cannot perform the correct operation

when reading during write operation, or when writing during read

operation.

Timers A and B are real time output port timers. For details, refer to

the section "Real time output port".

qTimer X, Timer Y

Timer X and Y are independent 16-bit timers which can select

enable seven different operation modes each by the setting of their

mode registers. The related registers of timer X and Y are listed

below. The following register abbreviations are used:

• Timer XY control register (TXYCON: address 001416)

• Port P4 direction register (P4D: address 000916)

• Port P5 direction register (P5D: address 000B16)

• Timer X (low-order) (TXL: address 002016)

• Timer X (high-order) (TXH: address 002116)

• Timer Y (low-order) (TYL: address 002216)

• Timer Y (high-order) (TYH: address 002316)

• Timer X mode register (TXM: address 002716)

• Timer Y mode register (TYM: address 002816)

• Interrupt edge selection register (INTEDGE: address 003A16)

• Interrupt request register 1 (IREQ1: address 003C16)

• Interrupt request register 2 (IREQ2: address 003D16)

• Interrupt control register 1 (ICON1: address 003E16)

• Interrupt control register 2 (ICON2: address 003F16)

For details, refer to the structures of each register.

The following is an explanation of the seven modes:

(1) Timer • event counter mode

ŒTimer mode

• Mode selection

This mode can be selected by setting "000" to the following bits.

Timer X operating mode bit (bits 2 to 0) of TXM

Timer Y operating mode bit (bits 2 to 0) of TYM

• Count source selection

In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be

selected as the count source.

In low-speed mode the count source is f(XCIN).

A count source is selected by the following bit.

Timer X count source selection bit (bits 7 and 6) of TXM

Timer Y count source selection bit (bits 7 and 6) of TYM

• Interrupt

When an underflow is generated, the corresponding timer X

interrupt request bit (b4) or timer Y interrupt request bit (b5) of IREQ1

is set to "1".

• Explanation of operation

After reset release, timer X stop control bit (b0) and timer Y stop

control bit (b1) of TXYCON are set to "1"and the timer stops.

During timer stop, a timer value written to the timer X or timer Y

is set by writing data to the corresponding timer latch and

timer at the same time. The timer operation is started by setting the

bits 0 or 1 of TXYCON to "0". When the timer reaches "000016", an

underflow occurs with the next count pulse. Then the contents of

the timer latch is reloaded into the timer and the timer continues

down-counting. For changing a timer value during count operation,

a latch value must be changed by writing data only to the

corresponding latch first. Then the timer is reloaded with the new

latch value at the next underflow.

Event counter mode

• Mode selection

This mode can be selected by the following sequence.

1. Set "000" to the timer X operating mode bit (bits 2 to 0) of TXM,

or to the timer Y operating mode bit (bits 2 to 0) of TYM.

2. Select an input signal from the CNTR0 pin (in case of timer X ;

set "11" to bits 7 and 6 of TXM), or from the CNTR1 pin (in case

of timer Y ; set "11" to bits 7 and 6 of TYM) as a count source.

The valid edge for the count operation is selected by the CNTR0/

CNTR1 active edge switch bit (b5) of TXM or TYM: if set to "0",

counting starts with the rising edge or if set to "1", counting starts

with the falling edge.

• Interrupt

The interrupt generation at underflow is the same as already

explained for the timer mode.

• Explanation of operation

The operation is the same as already explained for the timer mode.

In this mode, the double-function port of CNTR0/CNTR1 pin must

be set to input.

Figure 19 shows the timing chart for the timer • event counter mode.

(2) Pulse output mode

• Mode selection

This mode can be selected by setting "001" to the following bits.

Timer X operating mode bit (bits 2 to 0) of TXM

Timer Y operating mode bit (bits 2 to 0) of TYM

• Count source selection

In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be

selected as the count source.

In low-speed mode the count source is f(XCIN).

• Interrupt

The interrupt generation at underflow is the same as already

explained for the timer mode.

• Explanation of operation

Counting operation is the same as in timer mode. Moreover the

pulse which is inverted each time the timer underflows is output

from CNTR0/CNTR1 pin. When the CNTR0/CNTR1 active edge

switch bit (b5) of TXM or TYM is "0", output starts with "H" level.

When set to "1", output starts with "L" level.

19

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