VSC6501 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC6501

and Cable Driver at 1.485 Gb/s SMPTE-292M Reclocker

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

SMPTE-292M Reclocker and

Cable Driver at 1.485 Gb/s

Advance Product Information

VSC6501

Table 3: Pin Identification

Pin #

Name

2

292M

Status Output

Description

4

50

64

24

3,7,8,9,11

12,13,47,46

45,43,42,41

40,38,37,36,30

26

34

27

25

21,22

56,54

60,58

52,62

53,61

29

31

33

16,17

49,19

1

20,23,28,57,51

5,10,39,44

63

18

55,59

14,32,35,48

15

BYPASS

VSS

VDD

SCREN

Control Input to BYPASS CRU.

Connect with 10k resistor to appropriate signal.

INPUT - TTL: When HIGH, enables scrambling in Serializer/Deserializer modes

NC

No Connect: Leave these pins floating

FRAME

OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output which,

when HIGH, indicates that a FRAME synchronization event is on D[0:19].

LINE

OUTPUT - TTL: In Deserializer and Deserializer/Reclocker modes, this is an output which,

when HIGH, indicates that a LINE synchronization event is on D[0:19].

HANC

OUTPUT- TTL: Output which is HIGH during the Horizontal Blanking period between

EAV and SAV.

1.001

OUTPUT - TTL: When HIGH, indicates that a valid receive signal is present on IP/IN and

that the SMPTE-292M incoming data is greater than 500ppm from 20xREFCLK.

SDI, SDI INPUT - Differential. Serial input to CRU.

SDO0, SDO0 OUTPUT - Differential. High Speed Cable Driver output.

SDO1, SDO1 Serial output from the Reclocker or SDI, SDI input buffer.

ISET0, ISET1 Connect resistor to ground to set the output swing of SDO0, SDO1

OE0, OE1 INPUT - TTL. Output enable pins for SDO0 and SDO1. Enabled when high for each output.

REFCLK

INPUT - TTL. REFerence CLocK at 74.25 MHz. This is the input to the CMU and times

D[19:0] in Serializer Mode.

RCLK

OUTPUT - TTL: Output clock. In Serializer and Reclocker Mode, this is a buffered version

of REFCLK. In Deserializer Mode, this is the recovered clock used to time D[19:0]

SIGDET

OUTPUT - TTL. An analog signal detect output which, when HIGH, indicates that the SDI

input contains a valid SMPTE-292M amplitude signal.

CAP0, CAP1 Analog I/O: Loop Filter Capacitor, 0.1uF nominal, 3V swing maximum

TEST1, TEST2 INPUT - TTL. LOW for factory test, HIGH for normal operation.

V53

INPUT - POWER: This power supply would normally be 3.3V. If 5V tolerance is required,

this pin should be connected to 5V supply.

VDDD

Power Supply. 3.3V Supply for digital logic.

VDDT

TTL I/O Power Supply.

VREF

Voltage Reference Input. If used, this is biased to 1.25V.

VDDA

Analog Power Supply. 3.3V for Clock Multiplier PLL. Bypass to pin 15.

VSSP

Ground for High Speed Outputs

VSST

TTL I/O Ground

VSSA

Analog Ground Bypass to pin 18.

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52310-0, Rev. 2.0

4/10/00

Share Link: