VSC6511RC(2000) 查看數據表（PDF） - Vitesse Semiconductor

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VSC6511RC
(Rev.:2000)

Deserializer/Reclocker at 1.485Gb/s SMPTE-292M Serializer, Deserializer, and

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6511

SMPTE-292M Serializer, Deserializer, and

Deserializer/Reclocker at 1.485Gb/s

REFCLK

Figure 8: REFCLK Timing Waveforms: All Modes

TL

TH

TR

VIH(MIN)

VIL(MAX)

Table 6: Reference Clock Requirements *

Parameters

Description

Min Max Units

Conditions

FR

Frequency Range

FO

Frequency Offset

DC

REFCLK duty cycle

TH, TL

REFCLK high/low times

TR

REFCLK rise

Note: The PLL locks to the rising edge of REFCLK.

73.75 74.50

-1000 1000

-15 +15

3.0

—

—

2.0

MHz

ppm.

%

ns.

ns.

Will accept both 74.176/74.25MHz

Difference in REFCLK frequencies

between the transmitting and

receiving VSC6511s.

Measured at 1.5V

Measured between VIL(MAX) to

VIL(MAX) or VIH(MIN) to VIH(MIN)

Between VIL(MAX) and VIH(MIN)

Figure 9: RCLK Timing Waveforms*

RCLK

TL

TH

TR

VIH(MIN)

VIL(MAX)

Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode

Parameters

FOFFSET

Description

RCLK Frequency offset from

REFCLK

Min Max Units

-1.0 +1.0

%

DC

RCLK duty cycle - 40% / 60% -5

+5

%

TH

RCLK high times

3

—

ns.

TL

RCLK low times

5.9

—

ns.

TR

RCLK rise/fall time

—

1.5

ns.

Note: The RCLK output from the CRU is 40% high and 60% low by design.

Conditions

Maximum deviation when the CRU is

not locked. Deserializer Mode.

Measured at 1.5V. Deserializer Mode

and Deserializer/Reclocker Mode.

Measured between VIH(MIN) to

VIH(MIN)

Measured between VIL(MAX) to

VIL(MAX)

Between VIL(MAX) and VIH(MIN)

G52311-0, Rev. 2.0

4/10/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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