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TZA3004HL/C3 查看數據表(PDF) - Philips Electronics

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TZA3004HL/C3 Datasheet PDF : 24 Pages
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Philips Semiconductors
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
Objective specification
TZA3004HL
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
ta
td
BERLOS
LOS assert time
LOS de-assert time
LOS assert Bit Error Rate
LOS de-assert Bit Error Rate
note 10
0.1
µs
10
µs
5 ⋅10−2
BER
1 ⋅10−3
BER
PLL Characteristics
tacq
acquisition time
Jtol(p-p)(5) jitter tolerance (peak-to-peak)
TDR
transitionless data run
CREF = 19.44 MHz
CREF = 38.88 MHz
STM1/OC3 mode
f = 6.5 kHz
f = 65 kHz
f = 1 MHz
STM4/OC12 mode
f = 25 kHz
f = 100 kHz
f = 250 kHz
f = 1 MHz
f = 5 MHz
note 6
50
200 µs
100 200 µs
1.5
>5
UI
0.15 1.3
UI
0.15 0.8
UI
1.5
>5
UI
0.7
3
UI
0.15 1.3
UI
0.15 0.50
UI
0.15 0.35
UI
2000
bits
Notes
1. Typical supply voltage for the voltage regulator is 4.5 V (see Fig.4).
2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value. (true
differential excitation)
3. The specified input voltage range is the guaranteed and tested range for proper operation; BER <10-10.
4. An input sensitivity for BER <10-10 of 7 mVpp is guaranteed. Typical input sensitivity for BER <10-10 is 2.5mVpp.
5. CML inputs are terminated internally using 50 on-chip resistors to ground (GND).
6. Output voltage range with default reference voltage on AREF (floating pin).
7. Output voltage range with adjustment of voltage on AREF (see section “Output amplitude reference (AREF)”).
8. Data to clock delay according to figure 7. Measured with 1010 data pattern, single ended output signals and rising
edge of COUT to DOUT or CLOOP to DLOOP. Note that small deviations from specified value are possible if
differentially measured.
9. External 10 kpull-up resistor to +3.3 V.
10. LOS assert/de-assert timing and BER level are for indication only. The values are neither production tested nor
guaranteed.
11. Measured according ITU specification G.958 on the OM5800 STM4 demoboard.
12. TDR is bitrate independent.
1998 Feb 09
12

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