TDAT021G2 查看數據表（PDF） - Agere -> LSI Corporation
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TDAT021G2 Datasheet PDF : 310 Pages
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Advisory
May 2001
TDAT042G5 Device Advisory
for Version 1 and 1A of the Device
UTOPIA (UT) (continued)
UT2. UTOPIA Clock Limitations
The maximum speed of the UTOPIA interface is 104 MHz. When operating at clock speeds greater than 52 MHz,
RxCLK[D:A] must be placed in source mode and will use the same external clock as the corresponding
TxCLK[D:A] clock. RxCLK[D:A] source mode is set by provisioning bit 6 (CLOCK_MODE_Rx) for channel A of the
UTOPIA receive provisioning registers (address 0x020F).
When operating at speeds less than 52 MHz, separate external clocks for RxCLK[D:A] and TxCLK[D:A] may be
used.
Workaround
This is informational only. No workaround is available for this condition.
Corrective Action
This condition will be addressed in future versions of the device. Design modifications will be directed towards
allowing a maximum interface speed of 104 MHz in all cases. Note that UTOPIA Level 3 clock architecture has
changed in the ATM Forum’s UTOPIA Level 3 specification as of the July 1998 version.
UT3. PMRST Register Value Invalid After Reset
The value in PMRST_PECTx[A—D] (addresses 0x020B through 0x020E) is invalid after reset until the second
PMRST clock period is completed. After the second PMRST, the register value is valid.
Workaround
Always have the system software execute a read of PMRST_PECTx as part of the system initialization following a
reset.
Corrective Action
This condition will be addressed in future versions of the device.
Agere Systems Inc.
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