VSC9111 查看數據表（PDF） - Vitesse Semiconductor
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VSC9111 Datasheet PDF : 14 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
SONET/SDH 2.5Gb/s
Transport Terminating Transceiver
Target Specification
VSC9111
Pin Definitions
Pin
RLCLK+/-
Name
I/O
Parallel Line Receive
Clock
I
RLIN[15..0]+/-
Parallel Line Receive
Data
I
RLPRTY+/-
Parallel Line Receive
Parity
I
RLFP+/-
RXRCLK
LOPC
Parallel Line Receive
Frame Pulse
I
Receive Reference
Clock
O
Loss of Optical
Carrier
I
CLKRSTEN
Clock Reset Enable I
TLCLK+/-
Parallel Line Transmit
Clock
I
TLCLKOUT+/-
Parallel Line Transmit
Looped Clock
O
TLOUT[15..0]
+/-
Parallel Line Transmit
Data
O
TLPRTY+/-
Parallel Line Transmit
Parity
O
Freq
Type
PECL
PECL
PECL
PECL
TTL
TTL
TTL
PECL
PECL
PECL
PECL
Description
Clock reference for the 2.5Gb/s receive flow carried in
RLIN[15..0]. The clock frequency is nominally 155.52MHz
equivalent to STS-48/STM-16 operation.
Parallel data bus for the incoming STS-48/STM-16 data
stream. RLIN[15] is the most significant bit. RLIN[15] is the
first arriving bit on the serial data stream. RLIN[15..0] is
sampled on the rising edge of RLCLK+.
Parity input (even/odd parity) for the parallel receive line
data, RLIN[15..0] (optionally include RLFP). RLPRTY is
sampled on the rising edge of RLCLK+.
Frame pulse for the receive line interface. RLFP can be used
instead of the internal framing circuit (based on A1A2
patterns) for synchronizing the receive processor. RLFP is
sampled on the rising edge of RLCLK+.
RLFP is intended for use in STS-192/STM-64 applications.
Reference clock derived from RLCLK in a 78MHz/38MHz/
19MHz/8kHz version.
LOPC is monitored and changes in the signal status may
cause generation of an interrupt. This allows monitoring of
optical failures via the device CPU interface. When LOPC is
asserted, the receive processor is optionally clocked by the
transmit clock (derived from TLCLK).
If CLKRSTEN is asserted, all primary clock outputs
(TXRCLK, RXRCLK, TXCLKOUT_[A..D] and
RXCLK_[A..D]) will halt during master reset. If
CLKRSTEN is deasserted, all primary clock outputs will be
running during device master reset.
Clock reference for the 2.5Gb/s transmit flow carried in
TLOUT[15..0]. The clock frequency is nominally
155.52MHz equivalent to STS-48/STM-16 operation.
Looped TLCLK signal. Timing for this clock is defined with
reference to the TLOUT data bus signals. The clock
frequency is nominally 155.52MHz equivalent to STS-48/
STM-16 operation (same as TLCLK).
Parallel data bus for the outgoing STS-48/ STM-16 data
stream. TLOUT[15] is the most significant bit.TLOUT[15] is
the first transmitted bit on the serial data stream.
TLOUT[15..0] is generated on the rising edge of the
incoming TLCLK+.
Parity output (even/odd parity) for the parallel transmit line
data, TLOUT[15..0] (optionally includes TLFP). TLPRTY is
generated on the rising edge of TLCLK+.
Page 4
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-589610/21/98
G52199-0, Rev. 1.2
3/8/99
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