FW32305 查看數據表（PDF） - Agere -> LSI Corporation

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FW32305

1394A PCI PHY/Link Open Host Controller Interface

Agere -> LSI Corporation 

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 2

October 2001

Table of Contents (continued)

Table

Page

Table 103. Asynchronous Context Control Register Description ........................................................................120

Table 104. Asynchronous Context Command Pointer Register ..........................................................................121

Table 105. Asynchronous Context Command Pointer Register Description ........................................................122

Table 106. Isochronous Transmit Context Control Register .................................................................................123

Table 107. Isochronous Transmit Context Control Register Description .............................................................124

Table 108. Isochronous Transmit Context Command Pointer Register ...............................................................125

Table 109. Isochronous Transmit Context Command Pointer Register Description ............................................126

Table 110. Isochronous Receive Context Control Register ..................................................................................127

Table 111. Isochronous Receive Context Control Register Description ...............................................................128

Table 112. Isochronous Receive Context Command Pointer Register ................................................................129

Table 113. Isochronous Receive Context Command Pointer Register Description .............................................130

Table 114. Isochronous Receive Context Match Register ...................................................................................131

Table 115. Isochronous Receive Context Match Register Description ................................................................132

Table 116. FW323 Vendor Specific Registers Description ...................................................................................133

Table 117. Isochronous DMA Control Registers Description ...............................................................................134

Table 118. Asynchronous DMA Control Registers Description ............................................................................135

Table 119. Link Registers Description ..................................................................................................................136

Table 120. ROM Format Description ....................................................................................................................137

Table 121. Absolute Maximum Ratings ................................................................................................................138

Table 122. Analog Characteristics ........................................................................................................................139

Table 123. Driver Characteristics .........................................................................................................................140

Table 124. Device Characteristics ........................................................................................................................140

Table 125. Switching Characteristics ...................................................................................................................141

Table 126. Clock Characteristics ..........................................................................................................................141

Table 127. ac Characteristics of Serial EEPROM Interface Signals ....................................................................141

Table 128. PHY Core Register Map for the Cable Environment ..........................................................................144

Table 129. PHY Core Register Fields for Cable Environment ..............................................................................145

Table 130. PHY Core Register Page 0: Port Status Page ...................................................................................147

Table 131. PHY Core Register Port Status Page Fields .....................................................................................148

Table 132. PHY Core Register Page 1: Vendor Identification Page ....................................................................149

Table 133. PHY Core Register Vendor Identification Page Fields .......................................................................149

6

Agere Systems Inc.

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