HEF4029B 查看數據表（PDF） - Philips Electronics

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HEF4029B

Synchronous up/down counter, binary/decade counter

Philips Electronics 

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Fig.11 Example of parallel clocking when cascading HEF4029B ICs.

Note

TC lines at all stages after the first may have a negative-going glitch pulse resulting from differential delays of different HEF4029B ICs. These

negative-going glitches do not affect proper HEF4029B operation; however if the TC signals are used to trigger other edge-sensitive logic devices,

such as flip-flops or counters, the TC signals should be gated with the clock signal using a 2-input OR gate such as HEF4071B.

Fig.12 Example of ripple clocking when cascading HEF4029B ICs. Ripple clocking mode: the up/down control can be changed at any count;

the only restriction on changing the up/down control is that the clock input to the first counting stage must be HIGH.

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