AD7834 查看數據表（PDF） - Analog Devices

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AD7834

LC2MOS Quad 14-Bit DACs

Analog Devices 

AD7834/AD7835

CONTROLLED POWER-ON OF THE OUTPUT STAGE

A block diagram of the output stage of the AD7834/AD7835 is

shown in Figure 21. It is capable of driving a load of 10 kΩ in

parallel with 200 pF. G1 to G6 are transmission gates used to

control the power-on voltage present at VOUT. G1 and G2 are also

used in conjunction with the CLR input to set VOUT to the user-

defined voltage present at the DSG pin.

G1

DAC

G2

G6

G3

G4

G5

R

VOUT

G1

DAC

G2

G6

G3

G4

G5

R

VOUT

DSG

Figure 23. Output Stage with VDD > 10 V and CLR Low

VOUT is disconnected from the DSG pin by the opening of G5

but tracks the voltage present at DSG via the unity gain buffer.

POWER-ON WITH LDAC LOW, CLR HIGH

DSG

Figure 21. Block Diagram of AD7834/AD7835 Output Stage

POWER-ON WITH CLR LOW, LDAC HIGH

The output stage of the AD7834/AD7835 is designed to allow

output stability during power-on. If CLR is kept low during

power-on, and power is applied to the part, G1, G4, and G6 are

open while G2, G3, and G5 are closed (see Figure 22).

G1

DAC

G6

VOUT

G3

G4

G2

G5

R

DSG

Figure 22. Output Stage with VDD < 10 V

In many applications of the AD7834/AD7835, LDAC is kept

continuously low, updating the DAC after each valid data

transfer. If LDAC is low when power is applied, G1 is closed and

G2 is open, connecting the output of the DAC to the input of the

output amplifier. G3 and G5 are closed and G4 and G6 are open,

connecting the amplifier as a unity gain buffer, as before. VOUT is

connected to DSG via G5 and R (a thin-film resistance between

DSG and VOUT) until VDD and VSS reach approximately ±10 V.

Then, the internal power-on circuitry opens G3 and G5 and

closes G4 and G6. This is the situation shown in Figure 24. At

this point, VOUT is at the same voltage as the DAC output.

G1

DAC

G6

VOUT

G3

G4

G2

G5

R

VOUT is kept within a few hundred millivolts of DSG via G5

and R. R is a thin-film resistor between DSG and VOUT. The

output amplifier is connected as a unity gain buffer via G3, and

the DSG voltage is applied to the buffer input via G2. The

amplifier output is thus at the same voltage as the DSG pin. The

output stage remains configured as in Figure 22 until the

voltage at VDD and VSS reaches approximately ±10 V. At this

point, the output amplifier has enough headroom to handle

signals at its input and has also had time to settle. The internal

power-on circuitry opens G3 and G5 and closes G4 and G6 (see

Figure 23). As a result, the output amplifier is connected in

unity gain mode via G4 and G6. The DSG voltage is still applied

to the noninverting input via G2. This voltage appears at VOUT.

DSG

Figure 24. Output Stage with LDAC Low

LOADING THE DAC AND USING THE CLR INPUT

When LDAC goes low, it closes G1 and opens G2 as in Figure 24.

The voltage at VOUT now follows the voltage present at the out-

put of the DAC. The output stage remains connected in this

manner until a CLR signal is applied. Then, the situation reverts

(see Figure 23). Once again, VOUT remains at the same voltage as

DSG until LDAC goes low. This reconnects the DAC output to

the unity gain buffer.

Rev. D | Page 17 of 28

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