9240LP 查看數據表（PDF） - MAXWELL TECHNOLOGIES
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9240LP Datasheet PDF : 18 Pages
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14-Bit, 10 MSPS Monolithic A/D Converter with LPT ASIC
9240LP
PARAMETER
TABLE 3. 9240LP DC SPECIFICATIONS
(AVDD = 5V, DVDD = 5V, DRVDD = 5V, RBIAS = 2KΩ, VREF = 2.5V,
VINA=VINB = ±2.5V DIFFERENTIAL INPUT CENTERED ON VREF(1.25V TO 3.75V ABSOLUTE)
TA = -55 TO +125°C, UNLESS OTHERWISE SPECIFIED)
SUBGROUPS
MIN
TYP1
MAX
UNIT
RESOLUTION
1
14
--
--
Bits min
MAX CONVERSION RATE
MAX REFERRED NOISE1
VREF= 1 V
VREF = 2.5V
ACCURACY2
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
INL3
DNL3
No Missing Codes
Zero Error (@ 25 °C)
Gain Error (@ 25 °C)1,4
Gain Error (@ 25 °C)5
9, 10, 11
10
--
--
MHz min
--
0.9
--
--
0.36
--
LSB rms
1, 2, 3
-3
1, 2, 3
-1
--
--
1
--
1
--
--
1
--
± 2.5
3
± 0.6
1.0
± 2.5
--
± 0.7
--
14
--
0.3
--
1.5
--
0.75
LSB
LSB
LSB
LSB
Bits Guaranteed
% FSR
% FSR
% FSR
TEMPERATURE DRIFT
Zero Error
Gain Error4
Gain Error5
1, 2, 3
--
3.0
--
--
20.0
--
--
5.0
--
ppm/°C
ppm/°C
ppm/°C
POWER SUPPLY REJECTION
1, 2, 3
--
--
0.1
% FSR
ANALOG INPUT1
Input Span (with VREF = 1.0 V)
(with VREF = 2.5 V)
Input (VINA OR VINB) Range
Input Capacitance
2
1, 2, 3
--
0
--
INTERNAL VOLTAGE REFERENCE1
Output Voltage (1V mode)
--
Output Voltage Tolerance (1 V Mode)
--
Output Voltage (2.5 V Mode)
--
Output Voltage Tolerance (2.5 V Mode)
--
Load Regulation VREF
--
Load Regulation LPTVREF6,7
--
REFERENCE INPUT RESISTANCE
1, 2, 3
--
--
--
--
5
--
AVDD -.25
16
--
1
--
--
± 14
2.5
--
--
± 35
10
--
--
10.0
5
--
V p-p
V p-p
V
pF
V
mV
V
mV
mV
mV
kΩ
01.10.05 REV 6
All data sheets are subject to change without notice 4
©2005 Maxwell Technologies
All rights reserved.
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