ISP1581 查看數據表（PDF） - Philips Electronics

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ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

7.8 DMA Interface and DMA Handler

The DMA block can be subdivided into two blocks: the DMA Handler and the DMA

Interface.

The firmware writes to the DMA Command register to start a DMA transfer (see

Table 28). The command opcode determines whether a generic DMA, PIO, MDMA or

UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as

used by the USB core. Upon receiving the DMA Command, the DMA Handler directs

the data from the internal RAM to the external DMA device or from the external DMA

device to the internal RAM.

The DMA Interface configures the timings and the DMA handshake. Data can be

transferred either using DIOR and DIOW strobes or by the DACK and DREQ

handshakes. The different DMA configurations are set up by writing to the DMA

Configuration register (see Table 33 and Table 34).

For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel

I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA).

For a generic DMA interface, the DMA modes that can be used are Generic DMA

(Slave) and MDMA (Master).

7.9 System Controller

The System Controller implements the USB power-down capabilities of the ISP1581.

Registers are protected against data corruption during wake-up following a ‘resume’

(from the ‘suspend’ state) by locking the write access until an unlock code has been

written in the “Unlock Device” register.

9397 750 09665

Product data

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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