A83C452 查看數據表（PDF） - Intel

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A83C452

UPI-452 CHMOS PROGRAMMABLE I/O PROCESSOR

Intel 

UPI-452

HC7

HC6

HC5

HC4

HC3

HC2

HC1

HC0

Enable Output FIFO Interrupt due to Underrun Error Condition Data Stream Command or Service

Request

1 e Enable

0 e Disable

Enable Input FIFO Interrupt due to Overrun Error Condition or Service Request

1 e Enable

0 e Disable

Enable the generation of the Interrupt due to Immediate Command Out being present

1 e Enable

0 e Disable

Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate

Command byte

1 e Enable

0 e Disable

Reset UPI-452

1 e Software RESET

0 e Normal Operation

(reserved)

Select between INTRQ and INTRQIN INTRQOUT as Request for Service interrupt signal when DMA is

disabled

1 e INTRQ

0 e INTRQIN or INTRQOUT

(reserved)

NOTES

A ‘1’ will be read from all SFR reserved locations except HCON SFR HC0 and HC2

‘reserved’ these locations are reserved for future use by Intel Corporation

2) Host Status SFR (HSTAT)

The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the

source of an external interrupt during polling Like the Slave Status SFR the Host Status SFR reflects the

current status of the FIFO-external host interface

Symbolic

Address

HSTAT

HST7 HST6 HST5 HST4

w x Output FIFO Status

Status On Reset

1

1

1

1

(MSB)

HST3 HST2 HST1 HST0

w Input FIFO Status x

1

10

1

1

(LSB)

Physical

Address

0E6H

21

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