ML4805 查看數據表（PDF） - Fairchild Semiconductor

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ML4805

Variable Feedforward PFC/PWM Controller Combo

Fairchild Semiconductor 

FUNCTIONAL DESCRIPTION (Continued)

operating ffrreeqquueennccyy ccaann ttyyppiiccaalllyybbeeaapppprrooxximimaateteddbbyy::

fOSC

=

1

t RAMP

(5)

EXAMMPPLLEE::

For the application circuit shown in the data sheet, with

the oscillator running at:

fOSC

=

100kHz

=

1

t RAMP

tRAMP = 0.51´ R T ´ CT = 1´ 10-5

Solving for RT x CT yields 2 x 10-4. Selecting standard

components values, CT = 270pF, and RT = 36.5kΩ.

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4805 is straightforward, but

there are several points which should be noted. FForemost

among these is its inherent synchronization to the PFC

section of tthhee ddeevviiccee.. The PWM is capable of current-

mode or voltage mode operation. In current-mode

applications, the PWM ramp (RAMP 2) is usually derived

directly from a current sensing resistor or current

transformer in the primary of the output stage, and is

thereby representative of the current flowing in the

converter’s output stage. DC ILLIIMMIIT, wwhich provides

cycle-by-cycle current limiting, is typically connected to

RAMP 22 iinn ssuucch aapppplliiccaattiioonnss.. FFor vvoltage-mode operation

or certain specialized applications, RAMP 2 can be

connected to a separate RC timing network to generate a

voltage ramp against which VDC will be compared. Under

these conditions, the use of voltage feedforward from the

PFC buss can assist in line regulation accuracy and

response. As in current mode operation, the DC ILLIMIT

input is used for output stage overcurrent protection.

No voltage error amplifier is included in the PWM stage

of the ML4805, as this function is generally performed on

the output ssiiddee ooff tthhee PPWWMM’’ss iissoollaattiioonn bboouunnddaarryy.. To

facilitate the design of optocoupler feedback circuitry, an

offset has been built iinnttoo tthhee PPWWMM’’s RAMP 22 iinnppuutt wwhhiicch

allows VDC to command a zero percent duty cycle for

input voltages below 1.25V.

PWM Current Limit

The DC ILIMIT pin is a direct input to tthhee ccycle-by-cycle

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1.5V, the output of the

PWM will be disabled until the output flip-flop is reset by

the clock pulse at the start of the next PWM power cycle.

ML4805

VIINN OK Comparator

The VIN OK comparator mmoonniitors tthhee DDCC oouuttppuutt ooff tthhee

PFC and inhibits tthhee PPWWMM iiff tthhiiss vvoollttaaggee oonn VFB is less

than its nominal 2.5V. Once this voltage reaches 2.5V,

which corresponds to the PFC output capacitor being

charged to its rated boost voltage, the soft-start

commences.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2

is generally used as the sampling point for a voltage

representing the current in the primmaarryy ooff tthhee PPWWMM’’s

output transformer, derived either by a current sensing

resistor or a current transformer. In voltage mode, it is the

input for a ramp voltage generated by a second set of

timing components (RRAMP22, CRAMP2), which will have a

minimum value of zero volts and should have a peak

value of approximately 5V. In voltage mode operation,

feedforward from the PFC output buss is an excellent way

to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the

external capacitor at SS. A current source of 25µA

supplies the charging current for the capacitor, and start-

up of the PWM begins at 11..2255VV. Start-up dellaay can be

programmed by the following equation:

C SS

=

t DELAY

×

25µA

1.25V

(6)

where CSS is the required soft start capacitance, and

tDELAY is the desired start--uupp ddeellaay.

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufficient output power for

the PWM sseeccttiioonn.. The PWM start-up delay should be at

least 5ms.

Solving for the minimum value of CSS:

C SS

=

5ms ×

25µA

1.25V

= 100nF

In the ML4805, the operating frequency of the PFC

section is fixed at 1/2 of tthhee PPWWMM''ss ooppeerraattiinngg ffrreeqquueennccyy.

This is done through the use of a 2:1 digitaall ffrreeqquueennccy

divider ("T" flip-flop) linking the two functional sections of

the IC.

REV. 1.1 3/9/2001

9

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