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MX812DW

VSR CODEC WITH DRAM CONTROL

MX-COM Inc  

VSR CODEC with DRAM CONTROL

6

MX812 PRELIMINARY INFORMATION

The Controlling System: C-BUS Hardware Interface

C-BUS is MX-COM's proprietary standard for the transmission of commands and data between a µController and MX-COM's

New Generation integrated circuits. C-BUS is designed for a low IC pin-count, flexibility in handling variable amounts of data,

and simplicity of system design and µController software.

It may be used with any µController, and can, if desired, take advantage of the hardware serial I/O functions built into many

types of µController. Because of this flexibility and because the BUS data-rate is determined solely by the µController, the

system designer can choose a µController appropriate to the overall system processing requirements.

Control of the functions and levels within the MX812 VSR Codec is by a group of Address/Commands and appended data

instructions from the system µController to set/adjust the functions and elements of the MX812. The use of these instructions

is detailed in the following paragraphs and tables.

Command

Address/Command (A/C) Byte

+

Assignment

Hex.

Binary

MSB

LSB

General Reset

01

00000001

Write to Mode Register

60

01100000 +

Read Status Register

61

01100001 +

Store/Play Page

62

01100010 +

Wait

63

01100011

Table 1 – C-BUS Address/Commands

Data

Byte/s

1 byte Instruction to Mode Register

1 byte Reply from Status Register

2 bytes Command

“Write to Mode Register”

– A/C 60H, followed by 1 byte of Command Data.

Interrupt Output – IE

Controls the MX812 IRQ output driver.

Sampling Rates – SR

The CVSD Codec sampling rates. Accurate rates depend

upon the applied Xtal/clock frequency (see Table 5).

Memory Size – MS

The MX812 can operate with 1 x 1Mbit, 2 x 1Mbit or

1 x 4Mbit of DRAM (see Figure 4).

Powersave – PS

Powersaves the CVSD Codec only. Logic functions and

DRAM refresh are maintained.

Decode/Encode – DE

The Codec and DRAM operational mode.“

“Play” or “Store”

Interrupts

The MX812's Interrupt Output is driven by the Status Bit 7 (IF)

when the Mode Register Bit7 (IE) is set to a “1.”

The IF bit and the Interrupt Output (If enabled) are set when

the Store/Play/Wait command Buffer is emptied (MT bit) by

transferring from the buffer to the DRAM control circuits.

and/or

The IF bit and the Interrupt Output (if enabled) are set when

a Store, Play or Wait command has finished and the Command

Buffer is empty.

The notes below illustrate the IRQ pin conditions:

IF Bit

IE Bit

IRQ

“0” cleared “0” disable

High Z

“0” cleared “1” enable

High Z

“1” Interrupt “0” disable

High Z

“1” Interrupt “1” enable V (logic “0”)

SS

Setting

Mode Bits

MSB

7

1

0

Transmitted to 812 First

Interrupt Output

Enable

Disable

6

Sampling Rate

1

63kb/s

0

32kb/s

5

Memory (DRAM) Size

1

Single 4Mbit

0

1 or 2 x 1Mbit

4

Powersave

1

CVSD Codec Powersaved

0

CVSD Codec Powered

3

Decode/Encode

1

Decode – Play Mode

0

Encode – Store Mode

210

000

Not Used

Set to ‘zeros’

Table 2 - Control Register

“General Reset” – A/C 01H

Upon Power-Up the “bits” in the MX812 registers will be

random (either “0” or “1”). A General Reset Command (01H)

will be required to “reset” all microcircuits on the C-BUS, and

has the following effect upon the MX812.

Clear all Mode Register bits to “0”

Status Register Bit 7 (IF) to “0”

Bits 5 and 6 (MT and I) to “1”

Halt any current Store, Play or Wait execution

Clear the Store/Play/Wait Command Buffer

© 1997 MX•COM Inc.

www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054

Doc. # 20480076.003

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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